From patchwork Wed Nov 4 08:05:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuichi Ito X-Patchwork-Id: 11879803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92E79C2D0A3 for ; Wed, 4 Nov 2020 08:11:28 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 182CD20735 for ; Wed, 4 Nov 2020 08:11:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="haA1on2g" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 182CD20735 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=fujitsu.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=mxmwopXiBNBnh1W6GeZcOdDZadOtrqx75t7HeCcSHrQ=; b=haA1on2grYUno/awxzjOvPx1F lX9PkKlm3WTqPeimDLXszj4e7HmK1u+rqakBYuKUbfJ4CnQ+52KMXStzHkMiHWrBUaaDQqgKGpEGd jdvqTp54zv0NkeCxnrvGqwFKAOxRUPeS94aYXPqleq4XlTdYhv6lW874hXSO+PzqZQCXe7GUN3TpV bw8aliH9sho91XpEcvDfmsSXABukkMGGa2h+GFGwcV+/3sIJ1wsfvH1t/z2bvJVRiwfxctcybb1uq WcUYdDXlHRiqRzUMGbe8DX78lhcYGqN94Vlgvb453nFLojyURxxmEG1X6Ej7hvYp71EMsXMY+f8rZ MMENlCY4Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaDsg-0005AS-Ny; Wed, 04 Nov 2020 08:10:58 +0000 Received: from esa4.hc1455-7.c3s2.iphmx.com ([68.232.139.117]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaDsT-000563-63 for linux-arm-kernel@lists.infradead.org; Wed, 04 Nov 2020 08:10:46 +0000 IronPort-SDR: wHq0k7RRuHjmk4GSoXpZMzdMcjKu37jib33/iFPhQatFMviAgJVG+sJLN6PBdtETQ3JLkVNkCO eBzzZ2Dz5swm/kdTGms2mblcvMCiN4KYZAJKGcqECb98ShwDkAmEZzOoqmdpYj88oSk2JPkfgm TUnZGWmL3rFUxP1U3YbSbkmZKzPA72b2+b1xqNT6MPxc/gP/XZZO/tIhrV3g372xDC98W12wpW cx1vBntI12oGkQj0DKSKoFEkhhKBKVpH/oVzEL/flog2zpmH84jp2mdDGWgsGkaqP4BcBxLhjh aJU= X-IronPort-AV: E=McAfee;i="6000,8403,9794"; a="2271267" X-IronPort-AV: E=Sophos;i="5.77,450,1596466800"; d="scan'208";a="2271267" Received: from unknown (HELO yto-r1.gw.nic.fujitsu.com) ([218.44.52.217]) by esa4.hc1455-7.c3s2.iphmx.com with ESMTP; 04 Nov 2020 17:10:41 +0900 Received: from yt-mxq.gw.nic.fujitsu.com (unknown [192.168.83.47]) by yto-r1.gw.nic.fujitsu.com (Postfix) with ESMTP id 8B018EC7AD for ; Wed, 4 Nov 2020 17:10:40 +0900 (JST) Received: from pumpkin.openstacklocal (pumpkin.fct.css.fujitsu.com [10.130.70.189]) by yt-mxq.gw.nic.fujitsu.com (Postfix) with ESMTP id 8E9E1AC0097 for ; Wed, 4 Nov 2020 17:10:39 +0900 (JST) Received: by pumpkin.openstacklocal (Postfix, from userid 1016) id 30A24B99B; Wed, 4 Nov 2020 17:08:01 +0900 (JST) From: Yuichi Ito To: maz@kernel.org, sumit.garg@linaro.org, tglx@linutronix.de, jason@lakedaemon.net, catalin.marinas@arm.com, will@kernel.org Subject: [PATCH v2 1/3] irqchip/gic-v3: Enable support for SGIs to act as NMIs Date: Wed, 4 Nov 2020 17:05:37 +0900 Message-Id: <20201104080539.3205889-2-ito-yuichi@fujitsu.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201104080539.3205889-1-ito-yuichi@fujitsu.com> References: <20201104080539.3205889-1-ito-yuichi@fujitsu.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201104_031045_730919_644F4D75 X-CRM114-Status: GOOD ( 13.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: From: Sumit Garg Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI handler update in case of SGIs. Also, enable NMI support prior to gic_smp_init() as allocation of SGIs as IRQs/NMIs happen as part of this routine. Signed-off-by: Sumit Garg --- drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 16fecc0..7010ae2 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -461,6 +461,7 @@ static u32 gic_get_ppi_index(struct irq_data *d) static int gic_irq_nmi_setup(struct irq_data *d) { struct irq_desc *desc = irq_to_desc(d->irq); + u32 idx; if (!gic_supports_nmi()) return -EINVAL; @@ -478,16 +479,22 @@ static int gic_irq_nmi_setup(struct irq_data *d) return -EINVAL; /* desc lock should already be held */ - if (gic_irq_in_rdist(d)) { - u32 idx = gic_get_ppi_index(d); + switch (get_intid_range(d)) { + case SGI_RANGE: + break; + case PPI_RANGE: + case EPPI_RANGE: + idx = gic_get_ppi_index(d); /* Setting up PPI as NMI, only switch handler for first NMI */ if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { refcount_set(&ppi_nmi_refs[idx], 1); desc->handle_irq = handle_percpu_devid_fasteoi_nmi; } - } else { + break; + default: desc->handle_irq = handle_fasteoi_nmi; + break; } gic_irq_set_prio(d, GICD_INT_NMI_PRI); @@ -498,6 +505,7 @@ static int gic_irq_nmi_setup(struct irq_data *d) static void gic_irq_nmi_teardown(struct irq_data *d) { struct irq_desc *desc = irq_to_desc(d->irq); + u32 idx; if (WARN_ON(!gic_supports_nmi())) return; @@ -515,14 +523,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d) return; /* desc lock should already be held */ - if (gic_irq_in_rdist(d)) { - u32 idx = gic_get_ppi_index(d); + switch (get_intid_range(d)) { + case SGI_RANGE: + break; + case PPI_RANGE: + case EPPI_RANGE: + idx = gic_get_ppi_index(d); /* Tearing down NMI, only switch handler for last NMI */ if (refcount_dec_and_test(&ppi_nmi_refs[idx])) desc->handle_irq = handle_percpu_devid_irq; - } else { + break; + default: desc->handle_irq = handle_fasteoi_irq; + break; } gic_irq_set_prio(d, GICD_INT_DEF_PRI); @@ -1708,6 +1722,7 @@ static int __init gic_init_bases(void __iomem *dist_base, gic_dist_init(); gic_cpu_init(); + gic_enable_nmi_support(); gic_smp_init(); gic_cpu_pm_init(); @@ -1719,8 +1734,6 @@ static int __init gic_init_bases(void __iomem *dist_base, gicv2m_init(handle, gic_data.domain); } - gic_enable_nmi_support(); - return 0; out_free: