| Message ID | 20201105135656.383350-5-maxime@cerno.tech (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/vc4: Rework the HVS muxing code | expand |
Am 05.11.20 um 14:56 schrieb Maxime Ripard: > The code that assigns HVS channels during atomic_check is starting to grow > a bit big, let's move it into a separate function. > > Reviewed-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> > Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > --- > drivers/gpu/drm/vc4/vc4_kms.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c > index ad69c70f66a2..bb2efc5d2d01 100644 > --- a/drivers/gpu/drm/vc4/vc4_kms.c > +++ b/drivers/gpu/drm/vc4/vc4_kms.c > @@ -662,13 +662,13 @@ static int vc4_load_tracker_obj_init(struct vc4_dev *vc4) > return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL); > } > > -static int > -vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) > +static int vc4_pv_muxing_atomic_check(struct drm_device *dev, > + struct drm_atomic_state *state) > { > unsigned long unassigned_channels = GENMASK(HVS_NUM_CHANNELS - 1, 0); > struct drm_crtc_state *old_crtc_state, *new_crtc_state; > struct drm_crtc *crtc; > - int i, ret; > + unsigned int i; Thanks for fixing the type. It's always itching me when people use signed types for counters and array indices. It's just... not right. :) If you want to be super-correct you might as well make it size_t. Anyway Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> > > /* > * Since the HVS FIFOs are shared across all the pixelvalves and > @@ -741,6 +741,18 @@ vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) > } > } > > + return 0; > +} > + > +static int > +vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) > +{ > + int ret; > + > + ret = vc4_pv_muxing_atomic_check(dev, state); > + if (ret) > + return ret; > + > ret = vc4_ctm_atomic_check(dev, state); > if (ret < 0) > return ret; >
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index ad69c70f66a2..bb2efc5d2d01 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -662,13 +662,13 @@ static int vc4_load_tracker_obj_init(struct vc4_dev *vc4) return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL); } -static int -vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) +static int vc4_pv_muxing_atomic_check(struct drm_device *dev, + struct drm_atomic_state *state) { unsigned long unassigned_channels = GENMASK(HVS_NUM_CHANNELS - 1, 0); struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct drm_crtc *crtc; - int i, ret; + unsigned int i; /* * Since the HVS FIFOs are shared across all the pixelvalves and @@ -741,6 +741,18 @@ vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) } } + return 0; +} + +static int +vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) +{ + int ret; + + ret = vc4_pv_muxing_atomic_check(dev, state); + if (ret) + return ret; + ret = vc4_ctm_atomic_check(dev, state); if (ret < 0) return ret;