diff mbox series

[V2,3/5] arm64: dts: imx8mn: add GPC node and power domains

Message ID 20201107140026.1974312-3-aford173@gmail.com (mailing list archive)
State New, archived
Headers show
Series [V2,1/5] dt-bindings: add defines for i.MX8MN power domains | expand

Commit Message

Adam Ford Nov. 7, 2020, 2 p.m. UTC 
This adds the DT nodes to describe the power domains available on the
i.MX8MN. There are more power domains, but the displaymix and mipi
power domains need a separate clock block controller which not yet
available, so this limits it to the HSIO, OTG and GPU domains.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
V2:  Fix missing includes
     Remove interrupt controller flag
     Remove domains which interact with blk-ctl

 arch/arm64/boot/dts/freescale/imx8mn.dtsi | 36 +++++++++++++++++++++++
 1 file changed, 36 insertions(+)

Comments

Krzysztof Kozlowski Nov. 8, 2020, 6:45 p.m. UTC | #1 
On Sat, Nov 07, 2020 at 08:00:23AM -0600, Adam Ford wrote:
> This adds the DT nodes to describe the power domains available on the
> i.MX8MN. There are more power domains, but the displaymix and mipi
> power domains need a separate clock block controller which not yet
> available, so this limits it to the HSIO, OTG and GPU domains.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> ---
> V2:  Fix missing includes
>      Remove interrupt controller flag
>      Remove domains which interact with blk-ctl
> 
>  arch/arm64/boot/dts/freescale/imx8mn.dtsi | 36 +++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index ee1790230490..c37dee13057a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -4,6 +4,8 @@ 
  */
 
 #include <dt-bindings/clock/imx8mn-clock.h>
+#include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -598,6 +600,40 @@  src: reset-controller@30390000 {
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx8mn-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_hsiomix: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
+						clocks = <&clk IMX8MN_CLK_USB_BUS>;
+					};
+
+					pgc_otg1: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_OTG1>;
+						power-domains = <&pgc_hsiomix>;
+					};
+
+					pgc_gpumix: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
+						clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+							 <&clk IMX8MN_CLK_GPU_SHADER_DIV>,
+							 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+							 <&clk IMX8MN_CLK_GPU_AHB>;
+						resets = <&src IMX8MQ_RESET_GPU_RESET>;
+					};
+				};
+			};
 		};
 
 		aips2: bus@30400000 {