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dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4966.eurprd04.prod.outlook.com (2603:10a6:20b:2::14) by AM6PR04MB5206.eurprd04.prod.outlook.com (2603:10a6:20b:12::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.22; Thu, 26 Nov 2020 11:16:41 +0000 Received: from AM6PR04MB4966.eurprd04.prod.outlook.com ([fe80::3cfc:a92e:75ad:ce4a]) by AM6PR04MB4966.eurprd04.prod.outlook.com ([fe80::3cfc:a92e:75ad:ce4a%3]) with mapi id 15.20.3611.025; Thu, 26 Nov 2020 11:16:41 +0000 From: Dong Aisheng To: devicetree@vger.kernel.org Subject: [PATCH RESEND v4 08/18] arm64: dts: imx8: add conn lpcg clocks Date: Thu, 26 Nov 2020 18:58:50 +0800 Message-Id: <20201126105900.26658-9-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20201126105900.26658-1-aisheng.dong@nxp.com> References: <20201126105900.26658-1-aisheng.dong@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0160.apcprd03.prod.outlook.com (2603:1096:4:c9::15) To AM6PR04MB4966.eurprd04.prod.outlook.com (2603:10a6:20b:2::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from b29396-OptiPlex-7040.ap.freescale.net (119.31.174.66) by SG2PR03CA0160.apcprd03.prod.outlook.com (2603:1096:4:c9::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3632.7 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: ZJc6TLHp7sI0SmRcaf354nK99ySjeYOpFaL5vKu+fWNNdOEeBvrrGVz3+lxLhaOejLstytxzfj0xsUyGSl+/rHuAUEqwgbXQaEhQet7BEA2BjoHXdI0h+IP2BnawkBYw/CrK1J/YVVnfNQoRUAVHO0vVA202DWgM4SDQ2DHP4n4G4fdhYzhul7KdHXpU3kkDyG39TTyqbOHLqVcq0cHdhwWUGiHHUtRw7POmWNEOKEiMbixO/tcXu94ovMy77m4ZpythWkiBBYm1Bkvzp3yhpLZXNeZQ4Hf3ZjyVJDQrvkytLnitm+73dX/4C8if+A38NiHxO/dlInTxw3xfigDLqsJ3Tk2C2t4Vhggo5XX8eW7t3Tf/FhqbMcxkp9vxBky3/TWiDF2Hcu+er8RB1UBnN68piwzhzlwyH5tmOHruE3uSfMJ7MVLYFsWTsfkh42oI4R2FAXtSV0NdseGc8PkImUyfvjHaE0xSXEBH2tg4OdNZ1x4GwVJgJ56ExseKVP96FvNlBU9UtEPZ3YR3tbXw7dmhQ5lmdoS3MAie7kmcyzl+r2VcU/Q/nP8heoZIrpHhqH8ankEwpa8tCsUrPRIMY1MvvzBznw1IxoKJtE3oix7Vo67PTP8bFA1o5Q9/Q44lPI1sr6xcet24ImuNwEDqSEjhup04pDZoma7EmnbO0s1r8oLTrZB/inlPxG/gch3YhxLvejH2iBN7aA1AR+5uRQDtwXEPM53yhLvCB32f1uMs7tz9f7whM+Wm1+zcJPRYVNqxS6Etm4mlhiGNyTifyOY/B24FBXi2D6vKV4BeJ9AQT2Ma4DeyMFzSM84SsC19+BUCgbw2v8yyuK1vZ6Ibdl+UNPlvbmKC5t0sL7fD9SIRMhzIPv1taWl6+FtkXVMVObbrj9Andg4hwUG7pFem9A== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c5045402-3299-4334-1800-08d891fcc034 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4966.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2020 11:16:41.7569 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: UnZ9YayGvtuemd/q8wUwp4T3l2FeeB2I2Mc3cSrkzg4ASEG8L2J6il4jg6/obf9l9Ofz52VCOu+CHg/Q2TE25Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB5206 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201126_061645_294201_762886BA X-CRM114-Status: GOOD ( 14.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dong Aisheng , Mark Rutland , linux-mmc@vger.kernel.org, Rob Herring , linux-imx@nxp.com, Sascha Hauer , Fabio Estevam , Shawn Guo , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add conn lpcg clocks Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- ChangeLog: v2->v3: * update to use clock-indices property instead of bit-offset property v1->v2: * Use old SCU clock binding temporarily to avoid build warning due to SCU clock cell will be changed to 2. * add power domain propertyv1->v2: --- .../boot/dts/freescale/imx8-ss-conn.dtsi | 104 +++++++++++++++++- 1 file changed, 101 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 8691a43882fd..4220a5cdc249 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -4,15 +4,34 @@ * Dong Aisheng */ +#include +#include + conn_subsys: bus@5b000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; - conn_lpcg: clock-controller@5b200000 { - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; + conn_axi_clk: clock-conn-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <333333333>; + clock-output-names = "conn_axi_clk"; + }; + + conn_ahb_clk: clock-conn-ahb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <166666666>; + clock-output-names = "conn_ahb_clk"; + }; + + conn_ipg_clk: clock-conn-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <83333333>; + clock-output-names = "conn_ipg_clk"; }; usdhc1: mmc@5b010000 { @@ -83,4 +102,83 @@ conn_subsys: bus@5b000000 { power-domains = <&pd IMX_SC_R_ENET_1>; status = "disabled"; }; + + /* LPCG clocks */ + conn_lpcg: clock-controller-legacy@5b200000 { + reg = <0x5b200000 0xb0000>; + #clock-cells = <1>; + }; + + sdhc0_lpcg: clock-controller@5b200000 { + reg = <0x5b200000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC0_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = , , + ; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; + }; + + sdhc1_lpcg: clock-controller@5b210000 { + reg = <0x5b210000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC1_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = , , + ; + clock-output-names = "sdhc1_lpcg_per_clk", + "sdhc1_lpcg_ipg_clk", + "sdhc1_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_1>; + }; + + sdhc2_lpcg: clock-controller@5b220000 { + reg = <0x5b220000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC2_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = , , + ; + clock-output-names = "sdhc2_lpcg_per_clk", + "sdhc2_lpcg_ipg_clk", + "sdhc2_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_2>; + }; + + enet0_lpcg: clock-controller@5b230000 { + reg = <0x5b230000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>, + <&clk IMX_CONN_ENET0_ROOT_CLK>, + <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + clock-indices = , , + , , + ; + clock-output-names = "enet0_ipg_root_clk", + "enet0_tx_clk", + "enet0_ahb_clk", + "enet0_ipg_clk", + "enet0_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_0>; + }; + + enet1_lpcg: clock-controller@5b240000 { + reg = <0x5b240000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>, + <&clk IMX_CONN_ENET1_ROOT_CLK>, + <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + clock-indices = , , + , , + ; + clock-output-names = "enet1_ipg_root_clk", + "enet1_tx_clk", + "enet1_ahb_clk", + "enet1_ipg_clk", + "enet1_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_1>; + }; };