From patchwork Mon Nov 30 10:26:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 11940119 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EC6EC64E8A for ; Mon, 30 Nov 2020 10:28:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 15B3320708 for ; Mon, 30 Nov 2020 10:28:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="P6n3QKd3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 15B3320708 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=Mmy5ty0NOt8F8V7J8vXJGrHYnmaM+bhU3l2RpoJzp5I=; b=P6n3QKd3YcAgY3+moqtD3618Hl DkX50+qX03I29H1pRNMtF/32oIWBuMaKl5TrS9J/ZNb+Fc3+tRurZVdudqqtqWycVWUNibbcHhjyN n1c829znWmifGThbYbSBxsnUeGkTRvPIp98swbEtLmdWCvwXHIzV+S8s5Z5ySlY4n8L1uo7u7Chzu cZ0i3InEf0kJpxaAmB4sZY+3x7UXqsqMXGxm2w+YI4twAWC2GE6Tf6/spx4bpvQuz4+mCqHwtzF7N MkV0TDWt/u5f2Etwo4q7LGpq20fGQjdsn2CXTP9kJKgaw0o6JssfJEJC8YBEOTewxuqedPFNZ9gou 4vUZyUYA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjgP6-0005YM-Mz; Mon, 30 Nov 2020 10:27:32 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjgP3-0005Wd-E7 for linux-arm-kernel@lists.infradead.org; Mon, 30 Nov 2020 10:27:30 +0000 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4Cl1cZ3qkgz76GW; Mon, 30 Nov 2020 18:26:54 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.52.130.129) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 30 Nov 2020 18:27:08 +0800 From: Shameer Kolothum To: , Subject: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support Date: Mon, 30 Nov 2020 10:26:39 +0000 Message-ID: <20201130102639.7504-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.52.130.129] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_052729_985895_E41855FE X-CRM114-Status: GOOD ( 16.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: maz@kernel.org, linuxarm@huawei.com, eric.auger@redhat.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org At present, the support for GICv2 backward compatibility on GICv3/v4 hardware is determined based on whether DT/ACPI provides a memory mapped phys base address for GIC virtual CPU interface register(GICV). This creates a problem that a Qemu guest boot with default GIC(GICv2) hangs when firmware falsely reports this address on systems that don't have support for legacy mode.  As per GICv3/v4 spec, in an implementation that does not support legacy operation, affinity routing and system register access are permanently enabled. This means that the associated control bits are RAO/WI. Hence use the ICC_SRE_EL1.SRE bit to decide whether hardware supports GICv2 mode in addition to the above firmware based check. Signed-off-by: Shameer Kolothum --- On Hisilicon D06, UEFI sets the GIC MADT GICC gicv_base_address but the GIC implementation on these boards doesn't have the GICv2 legacy support. This results in, Guest boot hang when Qemu uses the default GIC option. With this patch, the Qemu Guest with GICv2 now gracefully exits,  "qemu-system-aarch64: host does not support in-kernel GICv2 emulation" Not very sure there is a better way to detect this other than checking the SRE bit as done in this patch(Of course, we will be fixing the UEFI going forward). Thanks, Shameer --- drivers/irqchip/irq-gic-v3.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 16fecc0febe8..15fa1eea45e4 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1835,6 +1835,27 @@ static void __init gic_populate_ppi_partitions(struct device_node *gic_node) of_node_put(parts_node); } +/* SRE bit being RAO/WI implies no GICv2 legacy mode support */ +static bool __init gic_gicv2_compatible(void) +{ + u32 org, val; + + org = gic_read_sre(); + if (!(org & ICC_SRE_EL1_SRE)) + return true; + + val = org & ~ICC_SRE_EL1_SRE; + gic_write_sre(val); + + val = gic_read_sre(); + gic_write_sre(org); + + if (val & ICC_SRE_EL1_SRE) + return false; + + return true; +} + static void __init gic_of_setup_kvm_info(struct device_node *node) { int ret; @@ -1851,10 +1872,12 @@ static void __init gic_of_setup_kvm_info(struct device_node *node) &gicv_idx)) gicv_idx = 1; - gicv_idx += 3; /* Also skip GICD, GICC, GICH */ - ret = of_address_to_resource(node, gicv_idx, &r); - if (!ret) - gic_v3_kvm_info.vcpu = r; + if (gic_gicv2_compatible()) { + gicv_idx += 3; /* Also skip GICD, GICC, GICH */ + ret = of_address_to_resource(node, gicv_idx, &r); + if (!ret) + gic_v3_kvm_info.vcpu = r; + } gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; @@ -2164,7 +2187,7 @@ static void __init gic_acpi_setup_kvm_info(void) gic_v3_kvm_info.maint_irq = irq; - if (acpi_data.vcpu_base) { + if (gic_gicv2_compatible() && acpi_data.vcpu_base) { struct resource *vcpu = &gic_v3_kvm_info.vcpu; vcpu->flags = IORESOURCE_MEM;