| Message ID | 20201203132543.861591-3-maxime@cerno.tech (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/vc4: DSI improvements and BCM2711 support | expand |
Hi Maxime, On 03.12.20 14:25, Maxime Ripard wrote: > From: Dave Stevenson <dave.stevenson@raspberrypi.com> > > The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register > definitions were swapped, so trying to use more than a single data > lane failed as lane 1 would get powered down. > (In theory a 4 lane device would work as all lanes would remain > powered). > > Correct the definitions. > > Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> > Signed-off-by: Maxime Ripard <maxime@cerno.tech> Wouldn't this deserve a "Fixes: ..." and "Cc: stable@vger.kernel.org" tag, as this bug is present in all stable releases since this driver was introduced? I think it would be really helpful to have it backported. Thanks Frieder > --- > drivers/gpu/drm/vc4/vc4_dsi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c > index b1d8765795f1..bb316e6cc12b 100644 > --- a/drivers/gpu/drm/vc4/vc4_dsi.c > +++ b/drivers/gpu/drm/vc4/vc4_dsi.c > @@ -306,11 +306,11 @@ > # define DSI0_PHY_AFEC0_RESET BIT(11) > # define DSI1_PHY_AFEC0_PD_BG BIT(11) > # define DSI0_PHY_AFEC0_PD BIT(10) > -# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10) > +# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10) > # define DSI0_PHY_AFEC0_PD_BG BIT(9) > # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9) > # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8) > -# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8) > +# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8) > # define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4) > # define DSI_PHY_AFEC0_PTATADJ_SHIFT 4 > # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0) >
On Tue, 2020-12-08 at 09:34 +0100, Frieder Schrempf wrote: > Hi Maxime, > > On 03.12.20 14:25, Maxime Ripard wrote: > > From: Dave Stevenson <dave.stevenson@raspberrypi.com> > > > > The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register > > definitions were swapped, so trying to use more than a single data > > lane failed as lane 1 would get powered down. > > (In theory a 4 lane device would work as all lanes would remain > > powered). > > > > Correct the definitions. > > > > Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > > Wouldn't this deserve a "Fixes: ..." and "Cc: stable@vger.kernel.org" > tag, as this bug is present in all stable releases since this driver was > introduced? I think it would be really helpful to have it backported. Agree, this would be nice: Fixes: 4078f5757144 ("drm/vc4: Add DSI driver") With that, Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Regards, Nicolas
Hi, On Tue, Dec 08, 2020 at 09:34:05AM +0100, Frieder Schrempf wrote: > On 03.12.20 14:25, Maxime Ripard wrote: > > From: Dave Stevenson <dave.stevenson@raspberrypi.com> > > > > The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register > > definitions were swapped, so trying to use more than a single data > > lane failed as lane 1 would get powered down. > > (In theory a 4 lane device would work as all lanes would remain > > powered). > > > > Correct the definitions. > > > > Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > > Wouldn't this deserve a "Fixes: ..." and "Cc: stable@vger.kernel.org" tag, > as this bug is present in all stable releases since this driver was > introduced? I think it would be really helpful to have it backported. Sorry I forgot it. The patch is applied however and drm-misc-next doesn't get rebased, so I can't add it now. We can always send it for stable by hand though once it's in Linus' tree Maxime
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c index b1d8765795f1..bb316e6cc12b 100644 --- a/drivers/gpu/drm/vc4/vc4_dsi.c +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -306,11 +306,11 @@ # define DSI0_PHY_AFEC0_RESET BIT(11) # define DSI1_PHY_AFEC0_PD_BG BIT(11) # define DSI0_PHY_AFEC0_PD BIT(10) -# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10) +# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10) # define DSI0_PHY_AFEC0_PD_BG BIT(9) # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9) # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8) -# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8) +# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8) # define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4) # define DSI_PHY_AFEC0_PTATADJ_SHIFT 4 # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)