From patchwork Tue Dec 8 17:42:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicola Mazzucato X-Patchwork-Id: 11959177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7E2FC433FE for ; Tue, 8 Dec 2020 17:42:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8392523B3E for ; Tue, 8 Dec 2020 17:42:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8392523B3E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=h93fKl33uvknXrSlWzk2PovHUdLdWdXygsx8fgvMM7s=; b=a2xkl5y4YuQhe8PcOqZr41fPS 2CLWEjUXE866JRRINeX+HI5wJk0uzxR2l6vjV7ojjMc5t+GsMfSBTa2T/sC1g6NOYgepp8nyGVCrc mCkEzTR0WukY0ucCi081E83RNZ5q3Xz2P5jVc3OWPUUpo16nKYUO3Hv6zNWuPPpRhIIKlMrg3fn/t X0iZHoeof+OqccLwNiGih/VSx+pt1rO4HLz2Qmih8S6uDdKvzkoh46ijQ01899vxhrwjKQGMMdKOR +SVLx6loMATGjfJdry6qA2kbKVyn75k5qca4iIvTao7zGPO7QJXdqd/lkvoxc9N4dTW5TuII4mp1C 9NJ1n+44A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmgzi-0005bO-Uu; Tue, 08 Dec 2020 17:41:47 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmgzY-0005Y4-Uy for linux-arm-kernel@lists.infradead.org; Tue, 08 Dec 2020 17:41:38 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5238231B; Tue, 8 Dec 2020 09:41:28 -0800 (PST) Received: from ubuntu.cambridge.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 24CC53F68F; Tue, 8 Dec 2020 09:41:26 -0800 (PST) From: Nicola Mazzucato To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, sudeep.holla@arm.com, rjw@rjwysocki.net, vireshk@kernel.org, robh+dt@kernel.org, sboyd@kernel.org, nm@ti.com Subject: [PATCH v5 1/4] dt-bindings: opp: Allow empty OPP tables Date: Tue, 8 Dec 2020 17:42:26 +0000 Message-Id: <20201208174229.24323-2-nicola.mazzucato@arm.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201208174229.24323-1-nicola.mazzucato@arm.com> References: <20201208174229.24323-1-nicola.mazzucato@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201208_124137_371029_72C62504 X-CRM114-Status: GOOD ( 12.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chris.redpath@arm.com, daniel.lezcano@linaro.org, morten.rasmussen@arm.com, nicola.mazzucato@arm.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently the optional property opp-shared is used within an opp table to tell that a set of devices share their clock/voltage lines (and the OPP points). It is therefore possible to use an empty OPP table to convey only that information, useful in situations where the opp points are provided via other means (hardware. firmware, etc). Update the documentation to remark this additional case and provide an example. Signed-off-by: Nicola Mazzucato --- Documentation/devicetree/bindings/opp/opp.txt | 54 ++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt index 9847dfeeffcb..08b3da4736cf 100644 --- a/Documentation/devicetree/bindings/opp/opp.txt +++ b/Documentation/devicetree/bindings/opp/opp.txt @@ -65,7 +65,9 @@ Required properties: - OPP nodes: One or more OPP nodes describing voltage-current-frequency combinations. Their name isn't significant but their phandle can be used to - reference an OPP. + reference an OPP. These are mandatory except for the case where the OPP table + is present only to indicate dependency between devices using the opp-shared + property. Optional properties: - opp-shared: Indicates that device nodes using this OPP Table Node's phandle @@ -568,3 +570,53 @@ Example 6: opp-microvolt-, opp-microamp-: }; }; }; + +Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware, +distinct clock controls but two sets of clock/voltage/current lines. + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + next-level-cache = <&A53_L2>; + clocks = <&dvfs_controller 0>; + operating-points-v2 = <&cpu_opp0_table>; + }; + cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + next-level-cache = <&A53_L2>; + clocks = <&dvfs_controller 1>; + operating-points-v2 = <&cpu_opp0_table>; + }; + cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x102>; + next-level-cache = <&A53_L2>; + clocks = <&dvfs_controller 2>; + operating-points-v2 = <&cpu_opp1_table>; + }; + cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x0 0x103>; + next-level-cache = <&A53_L2>; + clocks = <&dvfs_controller 3>; + operating-points-v2 = <&cpu_opp1_table>; + }; + + }; + + cpu_opp0_table: opp0_table { + compatible = "operating-points-v2"; + opp-shared; + }; + + cpu_opp1_table: opp1_table { + compatible = "operating-points-v2"; + opp-shared; + }; +};