[v2] clk: mediatek: Remove MT8192 unused clock

Commit Message

Tinghan Shen Dec. 9, 2020, 8:39 a.m. UTC

From: "Tinghan Shen" <[e-mail]>

Remove MT8192 sspm clock

Signed-off-by: Tinghan Shen <[e-mail]>
---
v2: resend patch to linux-mediatek because blocked by wrong mail setting.  

This patch depends on series "Mediatek MT8192 clock support"[1].

[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=379955 

---
 drivers/clk/mediatek/clk-mt8192.c | 15 ---------------
 1 file changed, 15 deletions(-)

Comments

Stephen Boyd Dec. 17, 2020, 8:55 a.m. UTC | #1

Quoting Tinghan Shen (2020-12-09 00:39:21)
> From: "Tinghan Shen" <[e-mail]>
> 
> Remove MT8192 sspm clock
> 
> Signed-off-by: Tinghan Shen <[e-mail]>
> ---
> v2: resend patch to linux-mediatek because blocked by wrong mail setting.  
> 
> This patch depends on series "Mediatek MT8192 clock support"[1].
> 
> [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=379955 

Can this be rolled into that series?

Weiyi Lu Dec. 22, 2020, 10:50 a.m. UTC | #2

On Thu, 2020-12-17 at 00:55 -0800, Stephen Boyd wrote:
> Quoting Tinghan Shen (2020-12-09 00:39:21)
> > From: "Tinghan Shen" <[e-mail]>
> > 
> > Remove MT8192 sspm clock
> > 
> > Signed-off-by: Tinghan Shen <[e-mail]>
> > ---
> > v2: resend patch to linux-mediatek because blocked by wrong mail setting.  
> > 
> > This patch depends on series "Mediatek MT8192 clock support"[1].
> > 
> > [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=379955 
> 
> Can this be rolled into that series?

Hi Tinghan,
Thank you. I'll roll this patch in my next version v6 of 8192 clocks
series.

Patch

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index 673dc60182f5..6983707e4ac9 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -403,15 +403,6 @@  static const char * const atb_parents[] = {
 	"mainpll_d5_d2"
 };
 
-static const char * const sspm_parents[] = {
-	"clk26m",
-	"mainpll_d5_d2",
-	"univpll_d5_d2",
-	"mainpll_d4_d2",
-	"univpll_d4_d2",
-	"mainpll_d6"
-};
-
 static const char * const dpi_parents[] = {
 	"clk26m",
 	"tvdpll_d2",
@@ -792,8 +783,6 @@  static const struct mtk_mux top_mtk_muxes[] = {
 		pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2),
 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
 		atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3),
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM_SEL, "sspm_sel",
-		sspm_parents, 0x090, 0x094, 0x098, 24, 3, 31, 0x008, 4),
 	/* CLK_CFG_9 */
 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel",
 		dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5),
@@ -1047,9 +1036,7 @@  static const struct mtk_gate infra_clks[] = {
 	GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12),
 	GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13),
 	GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14),
-	GATE_INFRA2(CLK_INFRA_SSPM, "infra_sspm", "sspm_sel", 15),
 	GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16),
-	GATE_INFRA2(CLK_INFRA_SSPM_BUS_H, "infra_sspm_bus_h", "axi_sel", 17),
 	GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18),
 	GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19),
 	GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20),
@@ -1068,8 +1055,6 @@  static const struct mtk_gate infra_clks[] = {
 	GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0),
 	GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1),
 	GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2),
-	GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self", "clk26m", 3),
-	GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self", "clk32k", 4),
 	GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5),
 	GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6),
 	GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7),