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IronPort-SDR: POpRHDGbTGiQBzzOtUaSd/N4rYawl+pre6aYmBSoYhsA/vYp5d4/1Qnm5wuxp4rFIJzgLl+BM/ xCttMzV+G0nh0wu1xobUF5Tvb0MmalWN8Ockm4BEoZeDNUSDJdZy9tYj0IEDbPmigxSDAsUQGb IJsLPG6oEsqzCNiRQL6frfae3fBJLOEkV/JwNkDJIG+pKfeYRrdN/bAZUerysJnBLAzle+evFR eBkIDroYOJgRDewuoHxKVw/QGW7Q/FfBmOT99KlnyMdfx2BwRsCARZqAbbDfu0o7X9piRQeQC6 K/Q= X-IronPort-AV: E=Sophos;i="5.78,405,1599548400"; d="scan'208";a="101529705" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Dec 2020 07:28:35 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 9 Dec 2020 07:28:34 -0700 Received: from soft-dev10.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 9 Dec 2020 07:28:32 -0700 From: Lars Povlsen To: Linus Walleij Subject: [PATCH -next 3/3] arm64: dts: sparx5: Add SGPIO irq support Date: Wed, 9 Dec 2020 15:27:53 +0100 Message-ID: <20201209142753.683208-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201209142753.683208-1-lars.povlsen@microchip.com> References: <20201209142753.683208-1-lars.povlsen@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201209_092835_899018_FA4D20A7 X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexandre Belloni , linux-kernel@vger.kernel.org, Microchip Linux Driver Support , linux-gpio@vger.kernel.org, Lars Povlsen , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This enables irq support for the SGPIO input banks, allowing SGPIO control signals to generate interrupts based on the signal state. This f.ex. allows the SFP driver to avoid polling of module detect, tx fault, loss of signal etc. control signals that may be connected via the SGPIO controller. Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 3bb4755e9f87..044063a9beae 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -277,13 +277,16 @@ sgpio0: gpio@61101036c { clocks = <&sys_clk>; pinctrl-0 = <&sgpio0_pins>; pinctrl-names = "default"; - reg = <0x6 0x1101036c 0x100>; + reg = <0x6 0x1101036c 0x118>; sgpio_in0: gpio@0 { compatible = "microchip,sparx5-sgpio-bank"; reg = <0>; gpio-controller; #gpio-cells = <3>; ngpios = <96>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; }; sgpio_out0: gpio@1 { compatible = "microchip,sparx5-sgpio-bank"; @@ -309,6 +312,9 @@ sgpio_in1: gpio@0 { gpio-controller; #gpio-cells = <3>; ngpios = <96>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; }; sgpio_out1: gpio@1 { compatible = "microchip,sparx5-sgpio-bank"; @@ -334,6 +340,9 @@ sgpio_in2: gpio@0 { gpio-controller; #gpio-cells = <3>; ngpios = <96>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; }; sgpio_out2: gpio@1 { compatible = "microchip,sparx5-sgpio-bank";