diff mbox series

[v5,18/25] coresight: etm4x: Expose trcdevarch via trcidr

Message ID 20201214173731.302520-19-suzuki.poulose@arm.com (mailing list archive)
State New, archived
Headers show
Series coresight: etm4x: Support for system instructions | expand

Commit Message

Suzuki K Poulose Dec. 14, 2020, 5:37 p.m. UTC
Expose the TRCDEVARCH register via the sysfs for component
detection. Given that the TRCIDR1 may not completely identify
the ETM component and instead need to use TRCDEVARCH, expose
this via sysfs for tools to use it for identification.

Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Mike Leach Dec. 16, 2020, 6:01 p.m. UTC | #1
Hi Suzuki

On Mon, 14 Dec 2020 at 17:38, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>
> Expose the TRCDEVARCH register via the sysfs for component
> detection. Given that the TRCIDR1 may not completely identify
> the ETM component and instead need to use TRCDEVARCH, expose
> this via sysfs for tools to use it for identification.
>
> Cc: Mike Leach <mike.leach@linaro.org>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 009818675928..277fd5bff811 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -2395,6 +2395,7 @@ coresight_etm4x_cross_read(trcidr10, TRCIDR10);
>  coresight_etm4x_cross_read(trcidr11, TRCIDR11);
>  coresight_etm4x_cross_read(trcidr12, TRCIDR12);
>  coresight_etm4x_cross_read(trcidr13, TRCIDR13);
> +coresight_etm4x_cross_read(trcdevarch, TRCDEVARCH);
>
>  static struct attribute *coresight_etmv4_trcidr_attrs[] = {
>         &dev_attr_trcidr0.attr,
> @@ -2410,6 +2411,7 @@ static struct attribute *coresight_etmv4_trcidr_attrs[] = {
>         &dev_attr_trcidr11.attr,
>         &dev_attr_trcidr12.attr,
>         &dev_attr_trcidr13.attr,
> +       &dev_attr_trcdevarch.attr,
>         NULL,
>  };
>

It makes far more sense for this to appear in the 'mgmt' group, per
the grouping in the Coresight spec. This would place it alongside the
other CoreSight management registers, including DEVID, and DEVTYPE
which is used with DEVARCH in the CoreSight UCI, . This is also
consistent with the CTI which places all three of these registers in
the 'mgmt' section.

Regards

Mike


> --
> 2.24.1
>
diff mbox series

Patch

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 009818675928..277fd5bff811 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -2395,6 +2395,7 @@  coresight_etm4x_cross_read(trcidr10, TRCIDR10);
 coresight_etm4x_cross_read(trcidr11, TRCIDR11);
 coresight_etm4x_cross_read(trcidr12, TRCIDR12);
 coresight_etm4x_cross_read(trcidr13, TRCIDR13);
+coresight_etm4x_cross_read(trcdevarch, TRCDEVARCH);
 
 static struct attribute *coresight_etmv4_trcidr_attrs[] = {
 	&dev_attr_trcidr0.attr,
@@ -2410,6 +2411,7 @@  static struct attribute *coresight_etmv4_trcidr_attrs[] = {
 	&dev_attr_trcidr11.attr,
 	&dev_attr_trcidr12.attr,
 	&dev_attr_trcidr13.attr,
+	&dev_attr_trcdevarch.attr,
 	NULL,
 };