[v2,3/4] arm64: dts: cn913x: add device trees for topology B boards

Message ID	20201217075542.12472-4-kostap@marvell.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=g+kj=FV=lists.infradead.org=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 410BA23434 From: <kostap@marvell.com> To: <linux-arm-kernel@lists.infradead.org> Subject: [PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards Date: Thu, 17 Dec 2020 09:55:41 +0200 Message-ID: <20201217075542.12472-4-kostap@marvell.com> In-Reply-To: <20201217075542.12472-1-kostap@marvell.com> References: <20201217075542.12472-1-kostap@marvell.com> MIME-Version: 1.0 Precedence: list Cc: tmn505@gmail.com, andrew@lunn.ch, jaz@semihalf.com, gregory.clement@bootlin.com, nadavh@marvell.com, robh+dt@kernel.org, Konstantin Porotchkin <kostap@marvell.com>, stefanc@marvell.com, mw@semihalf.com, bpeled@marvell.com, sebastian.hesselbarth@gmail.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
Series	DTS updates for Marvell Armada CN913x platforms \| expand [v2,0/4] DTS updates for Marvell Armada CN913x platforms [v2,1/4] Documentation/bindings: phy: update references to cp11x [v2,2/4] arch/arm64/boot/dts/marvell: fix NAND partitioning scheme [v2,3/4] arm64: dts: cn913x: add device trees for topology B boards [v2,4/4] arm64: dts: add support for Marvell cn9130-crb platform

diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 3e5f2e7a040c..d9b924a63d89 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -13,6 +13,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb -dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb -dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb -dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb +dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-A.dtb +dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb +dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-A.dtb +dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb +dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-A.dtb +dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-A.dts b/arch/arm64/boot/dts/marvell/cn9130-db-A.dts new file mode 100644 index 000000000000..adb3a67a20b1 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-db-A.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marvell International Ltd. + * + * Device tree for the CN9130-DB board. + */ + +#include "cn9131-db.dtsi" + +/ { + model = "Marvell Armada CN9130-DB setup A"; +}; + +/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash. + * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated + * simultaneously. When SPI controller is enabled, NAND should be disabled. + */ + +&cp0_spi1 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-B.dts b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts new file mode 100644 index 000000000000..57e41cacd483 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Device tree for the CN9130-DB board (setup "B"). + */ + +#include "cn9130-db.dtsi" + +/ { + model = "Marvell Armada CN9130-DB setup B"; +}; + +/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash. + * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated + * simultaneously. When NAND controller is enabled, SPI1 should be disabled. + */ + +&cp0_nand_controller { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi similarity index 99% rename from arch/arm64/boot/dts/marvell/cn9130-db.dts rename to arch/arm64/boot/dts/marvell/cn9130-db.dtsi index d24294888400..8de3a552b806 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dts +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -10,8 +10,6 @@ #include <dt-bindings/gpio/gpio.h> / { - model = "Marvell Armada CN9130-DB"; - chosen { stdout-path = "serial0:115200n8"; }; @@ -235,6 +233,7 @@ /* U54 */ &cp0_nand_controller { + status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&nand_pins &nand_rb>; @@ -306,7 +305,7 @@ /* U55 */ &cp0_spi1 { - status = "okay"; + status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&cp0_spi0_pins>; reg = <0x700680 0x50>; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-A.dts b/arch/arm64/boot/dts/marvell/cn9131-db-A.dts new file mode 100644 index 000000000000..a60fdee79bf8 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9131-db-A.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marvell International Ltd. + * + * Device tree for the CN9131-DB board. + */ + +#include "cn9131-db.dtsi" + +/ { + model = "Marvell Armada CN9131-DB setup A"; +}; + +/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash. + * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated + * simultaneously. When SPI controller is enabled, NAND should be disabled. + */ + +&cp0_spi1 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-B.dts b/arch/arm64/boot/dts/marvell/cn9131-db-B.dts new file mode 100644 index 000000000000..94e01192aed1 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9131-db-B.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Device tree for the CN9131-DB board (setup "B"). + */ + +#include "cn9131-db-A.dts" + +/ { + model = "Marvell Armada CN9131-DB setup B"; +}; + +/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash. + * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated + * simultaneously. When NAND controller is enabled, SPI1 should be disabled. + */ + +&cp0_nand_controller { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi similarity index 97% rename from arch/arm64/boot/dts/marvell/cn9131-db.dts rename to arch/arm64/boot/dts/marvell/cn9131-db.dtsi index 3c975f98b2a3..82471a83ad6d 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dts +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi @@ -1,14 +1,13 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (C) 2019 Marvell International Ltd. + * Copyright (C) 2020 Marvell International Ltd. * * Device tree for the CN9131-DB board. */ -#include "cn9130-db.dts" +#include "cn9130-db.dtsi" / { - model = "Marvell Armada CN9131-DB"; compatible = "marvell,cn9131", "marvell,cn9130", "marvell,armada-ap807-quad", "marvell,armada-ap807"; diff --git a/arch/arm64/boot/dts/marvell/cn9132-db-A.dts b/arch/arm64/boot/dts/marvell/cn9132-db-A.dts new file mode 100644 index 000000000000..1f2e6377afc3 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9132-db-A.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marvell International Ltd. + * + * Device tree for the CN9132-DB board. + */ + +#include "cn9132-db.dtsi" + +/ { + model = "Marvell Armada CN9132-DB setup A"; +}; + +/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash. + * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated + * simultaneously. When SPI controller is enabled, NAND should be disabled. + */ + +&cp0_spi1 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/marvell/cn9132-db-B.dts b/arch/arm64/boot/dts/marvell/cn9132-db-B.dts new file mode 100644 index 000000000000..7137a6f22d0f --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9132-db-B.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marvell International Ltd. + * + * Device tree for the CN9132-DB board. + */ + +#include "cn9132-db.dtsi" + +/ { + model = "Marvell Armada CN9132-DB setup B"; +}; + +/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash. + * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated + * simultaneously. When NAND controller is enabled, SPI1 should be disabled. + */ + +&cp0_nand_controller { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dts b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi similarity index 97% rename from arch/arm64/boot/dts/marvell/cn9132-db.dts rename to arch/arm64/boot/dts/marvell/cn9132-db.dtsi index 4ef0df3097ca..0c2d9f57318b 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-db.dts +++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi @@ -1,14 +1,13 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (C) 2019 Marvell International Ltd. + * Copyright (C) 2020 Marvell International Ltd. * * Device tree for the CN9132-DB board. */ -#include "cn9131-db.dts" +#include "cn9131-db.dtsi" / { - model = "Marvell Armada CN9132-DB"; compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130", "marvell,armada-ap807-quad", "marvell,armada-ap807";

[v2,3/4] arm64: dts: cn913x: add device trees for topology B boards

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