clk: mediatek: Remove unused MT8192 mcupm clock

Commit Message

Tinghan Shen Dec. 22, 2020, 5:35 a.m. UTC

From: "TingHan Shen" <[e-mail]>

Remove unused MT8192 mcupm clock

Signed-off-by: TingHan Shen <[e-mail]>
---
This patch depends on series "Mediatek MT8192 clock support"[1].

[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=379955
---
 drivers/clk/mediatek/clk-mt8192.c | 9 ---------
 1 file changed, 9 deletions(-)

Patch

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index 673dc60182f5..80df1903bd58 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -649,12 +649,6 @@  static const char * const aes_msdcfde_parents[] = {
 	"univpll_d6"
 };
 
-static const char * const mcupm_parents[] = {
-	"clk26m",
-	"mainpll_d6_d4",
-	"mainpll_d6_d2"
-};
-
 static const char * const sflash_parents[] = {
 	"clk26m",
 	"mainpll_d7_d8",
@@ -856,8 +850,6 @@  static const struct mtk_mux top_mtk_muxes[] = {
 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
 		aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
 	/* CLK_CFG_16 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, "mcupm_sel",
-		mcupm_parents, 0x110, 0x114, 0x118, 0, 2, 7, 0x00c, 2),
 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
 		sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
 };
@@ -983,7 +975,6 @@  static const struct mtk_gate infra_clks[] = {
 	GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
 	GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
 	GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
-	GATE_INFRA0(CLK_INFRA_MCUPM, "infra_mcupm", "mcupm_sel", 7),
 	GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
 	GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
 	GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),