From patchwork Tue Jan 5 00:11:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Boichat X-Patchwork-Id: 11997837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B329FC433DB for ; Tue, 5 Jan 2021 00:13:45 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 68ABB2255F for ; Tue, 5 Jan 2021 00:13:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 68ABB2255F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DyaPZ5csepsXFDBGvz0cGEXLO3y5KMEwFf7xyFZuG6k=; b=d0qGbMP8oy6c+vPy1upyNUbk4 Z/ULgdmLvhtDPWvhMPErPKapvGsLh1RCFNZgA4eNEkvN9mewwRu1qUuzaBEK15TfzWGxJwp1KR1/g fKNS8Zf0lExfMPe59Z3xtXSq8WQ6ReajyS8JJw4glk6VmZDsaRDobfcogQuyznPO93zTL1ptUDmud Y75K0fYGBSXJswkVxUG9qHpRX/BIbsPgaZnzXHQ6ZeedFcxDghvNDDrDDTse4h4xgGDfnX/U1ZHRG TKqlRCYbq6jVP66UHXIvpcG6TQJbQDLCUaPI0vfA7U5cj4824U5l77ercv8y+jET7KrDcC9Rk73Vj B/UJjNShg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kwZx0-0004wX-O8; Tue, 05 Jan 2021 00:11:50 +0000 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kwZwu-0004tE-TM for linux-arm-kernel@lists.infradead.org; Tue, 05 Jan 2021 00:11:47 +0000 Received: by mail-pj1-x1036.google.com with SMTP id n3so501968pjm.1 for ; Mon, 04 Jan 2021 16:11:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=83v+PIDFz4v63RCasvVFLcN6hsWhRSs54bQAuSfaBKY=; b=YMlWfKfda3IbjO0mredMNVECivKRj4iCQ50YMa0slRRD2FdvB9Nd2eue0G/0hv/lhZ cF6UeV6vGtnaaBmVPex/OK/gFirT+H1oKtE/ghkMPseheP16Jn5fM93PlJ1i0ofnZzcJ DCdxPNTKcIqQ4Uxus+BFYhJ2O0lQTJ5Zt3KS8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=83v+PIDFz4v63RCasvVFLcN6hsWhRSs54bQAuSfaBKY=; b=lMS7dx2c/2v9g0SjdPLIcw62gRK3hoTMQHAqPPQFICraGt1YIb7nUeEjbx1lww5u56 UCiSqnKXSY3cDdDU6FdeLulImQqrvIssKwVELRanjfcmiIUuMkmlpax4j3fsx19t4mF3 Kb9BrDC4RTDbsEiAIX0h0aXMfyql9ReN0NCMC9avU45Jt7LKIya2kRORjJbAipye2uvb 5+HYN92zE7Em1ESsAK1aQ2M4zvtSwYrsXeOsqRImLEAMTbroPcWXRst2mRljxzsIzXYf 1JDKmeBGxHJyenLiHcT9himfJ5O741QEYRoiWbOfNxNHjk6opsd5Pq46ryutOPnB4G9c l0EA== X-Gm-Message-State: AOAM532XHCCu44A6vYAAh4SB7vJLeaOfZ6sFQCKLSnKGb1SZ3QcIHE5p HZHLdeDxsC4Ps723kEAQfOVWFA== X-Google-Smtp-Source: ABdhPJzNxpv2C3vPqs/tfE1uF2x7hhes9tStP0ghXznDrgXLZWxAh/Q5Da1158TlY7IVg+RA0aocHg== X-Received: by 2002:a17:90b:4b11:: with SMTP id lx17mr1354992pjb.154.1609805502832; Mon, 04 Jan 2021 16:11:42 -0800 (PST) Received: from drinkcat2.tpe.corp.google.com ([2401:fa00:1:b:7220:84ff:fe09:41dc]) by smtp.gmail.com with ESMTPSA id bf3sm465620pjb.45.2021.01.04.16.11.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 16:11:42 -0800 (PST) From: Nicolas Boichat To: Rob Herring , Steven Price , Alyssa Rosenzweig Subject: [PATCH v6 2/4] arm64: dts: mt8183: Add node for the Mali GPU Date: Tue, 5 Jan 2021 08:11:17 +0800 Message-Id: <20210105081111.v6.2.I9f45f5c1f975422d58b5904d11546349e9ccdc94@changeid> X-Mailer: git-send-email 2.29.2.729.g45daf8777d-goog In-Reply-To: <20210105001119.2129559-1-drinkcat@chromium.org> References: <20210105001119.2129559-1-drinkcat@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210104_191145_019266_E451D555 X-CRM114-Status: GOOD ( 14.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , fshao@chromium.org, linux-kernel@vger.kernel.org, Rob Herring , boris.brezillon@collabora.com, linux-mediatek@lists.infradead.org, hsinyi@chromium.org, Matthias Brugger , hoegsberg@chromium.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a basic GPU node for mt8183. Signed-off-by: Nicolas Boichat --- The binding we use with out-of-tree Mali drivers includes more clocks, this is used for devfreq: the out-of-tree driver switches clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then switches clk_mux back to clk_main_parent: (see https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#423) clocks = <&topckgen CLK_TOP_MFGPLL_CK>, <&topckgen CLK_TOP_MUX_MFG>, <&clk26m>, <&mfgcfg CLK_MFG_BG3D>; clock-names = "clk_main_parent", "clk_mux", "clk_sub_parent", "subsys_mfg_cg"; (based on discussions, this probably belongs in the clock core) This only matters for devfreq, that is disabled anyway as we don't have platform-specific code to handle >1 supplies. Changes in v6: - Add gpu regulators to kukui dtsi as well. - Power domains are now attached to spm, not scpsys - Drop R-B. Changes in v5: - Rename "2d" power domain to "core2" (keep R-B again). Changes in v4: - Add power-domain-names to describe the 3 domains. (kept Alyssa's reviewed-by as the change is minor) Changes in v3: - No changes Changes in v2: - Use sram instead of mali_sram as SRAM supply name. - Rename mali@ to gpu@. arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 6 + .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 6 + arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 ++++++++++++++++++ 3 files changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index cba2d8933e79..0a8c2fad8e16 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -42,6 +42,12 @@ &auxadc { status = "okay"; }; +&gpu { + supply-names = "mali", "sram"; + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c_pins_0>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index bf2ad1294dd3..00d8e112cab9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -249,6 +249,12 @@ &cpu7 { proc-supply = <&mt6358_vproc11_reg>; }; +&gpu { + supply-names = "mali", "sram"; + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5b782a4769e7..5430e05e18a0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -964,6 +964,111 @@ mfgcfg: syscon@13000000 { #clock-cells = <1>; }; + gpu: gpu@13040000 { + compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; + reg = <0 0x13040000 0 0x4000>; + interrupts = + , + , + ; + interrupt-names = "job", "mmu", "gpu"; + + clocks = <&topckgen CLK_TOP_MFGPLL_CK>; + + power-domains = + <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, + <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, + <&spm MT8183_POWER_DOMAIN_MFG_2D>; + power-domain-names = "core0", "core1", "core2"; + + operating-points-v2 = <&gpu_opp_table>; + }; + + gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <625000>, <850000>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + opp-microvolt = <631250>, <850000>; + }; + + opp-340000000 { + opp-hz = /bits/ 64 <340000000>; + opp-microvolt = <637500>, <850000>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + opp-microvolt = <643750>, <850000>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + opp-microvolt = <650000>, <850000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <656250>, <850000>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <662500>, <850000>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + opp-microvolt = <675000>, <850000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <687500>, <850000>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <700000>, <850000>; + }; + + opp-580000000 { + opp-hz = /bits/ 64 <580000000>; + opp-microvolt = <712500>, <850000>; + }; + + opp-620000000 { + opp-hz = /bits/ 64 <620000000>; + opp-microvolt = <725000>, <850000>; + }; + + opp-653000000 { + opp-hz = /bits/ 64 <653000000>; + opp-microvolt = <743750>, <850000>; + }; + + opp-698000000 { + opp-hz = /bits/ 64 <698000000>; + opp-microvolt = <768750>, <868750>; + }; + + opp-743000000 { + opp-hz = /bits/ 64 <743000000>; + opp-microvolt = <793750>, <893750>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <825000>, <925000>; + }; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>;