From patchwork Fri Jan 8 12:04:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 12006535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06895C433E0 for ; Fri, 8 Jan 2021 12:13:13 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A36B023975 for ; Fri, 8 Jan 2021 12:13:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A36B023975 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=UTOhT5rp4nzReyBL4IhLbUiZGR5b1yaqfTrtPa5jL9w=; b=mx9XgPZ92pAGO556GphtLv/wR Q78+cctyTEbas/Ly1Fx1SJoVzbch/Y1w0QIFZLxCjINYWDTZcKnNOmmmLxxz0kGUziX2g1giuFLS1 je+fUi3wBAFbolrEo99ylEHbjiYTxGnWluvBXgQNl26BJ41X6Muvi8l8XnH0Q8wbzWXuUWv+IRVPe xGTA9TCJ23F3nNkBsaehiwzfTqfy7sLB3+zimQNy2EABIN5rTQhinY6GXlb3BxFDudphHv0u/FUk7 k5U+mstVtg1S34tZYCw+IkSHgLYP9yLCTwbV4jNphJlDd/bWBSfxSh7FMWkXDCXxI38nLDNq1O/DG Mrct4JYZg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxqbL-00046x-Kj; Fri, 08 Jan 2021 12:10:43 +0000 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxqWD-0002Wg-Oy for linux-arm-kernel@lists.infradead.org; Fri, 08 Jan 2021 12:05:34 +0000 Received: by mail-ej1-x630.google.com with SMTP id ce23so14181386ejb.8 for ; Fri, 08 Jan 2021 04:05:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zenOUjj7fqdHVMcIyrfHAw9wRuBqaP3SJknWkeDXfZ8=; b=wlIwJPCQ24PZZzMz7cbeyPcdVaAXTz2foB4Kk3y1hwQQaCWNLA9TMXqy0ZEgVpjIcI BAVKvvWTu2JAjoh/y4A9/ZF1j1Cv7UqH21XCIPiPG07/W+OfykDUoHwxfmb4j8K5j1A+ q9J3w1mlhE52BUcRq60nL475yHfh1cWN5bVeiow+FsuFipdIXzq1mDUj+SvPZCDL6VNd IsFKvRImamxAGNT/cM/p2xy+45yjFGnFB79ZvIKs9he/KWPbpTGgphC13ZLplo5wAsOS fM9dbs5uwQOqvmh1ZibfZTUe/MJEGuF+EcQnV3tWkVC18UuwyMO0pWDyV9Ju8tFDzeSY YI3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zenOUjj7fqdHVMcIyrfHAw9wRuBqaP3SJknWkeDXfZ8=; b=bbJMGlQ2/WuYQeTnP1ASvnzCv7Z99ZeD7svUhgU/ygCD5WAK2ixzl8hOWnw2KA0RSj rDhMeTJMVhNzZxTrnX+KqXU3PEe0ZcqAuIfng8cd4ojG+j1cqDzFLU8x1hFURpkhf3Cn CfZ27jR4pxlhNur4lEgk9MaRovGhOjGEMjI/XV4YJjxSk3sOyjg8LHbljGSdlKriWg/l P8xuPlp7z6U2UKISA0qWJ4ehXjbZR9y+zYuEHrkWH6BwvaEh4QslgOEtN17ypqTAS2Ea tUzoot5JzdqVgjCuW9tG/0WhfCn+N4Iln85yy+l5Qj35mfC5/QIyH/x16o6vTdSFqhcb lhCA== X-Gm-Message-State: AOAM531UrnHqNC5suqdYwxFrYqlXWdect901YOqC4mLqlOs5wOG4edNt 7hYsRcHA8PC1WKG8mRdgol8Zzg== X-Google-Smtp-Source: ABdhPJxl9WfyVp6H/rTQvYjnxl/ja0oMdb2MwIl78avaRgObY2HfUd3MYDBplw/hgwc4vfoGcbasVw== X-Received: by 2002:a17:906:3513:: with SMTP id r19mr2349595eja.445.1610107524864; Fri, 08 Jan 2021 04:05:24 -0800 (PST) Received: from localhost.localdomain ([2a02:2450:102f:d6a:bb2e:8b50:322a:1b9a]) by smtp.gmail.com with ESMTPSA id i18sm3674498edt.68.2021.01.08.04.05.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 04:05:24 -0800 (PST) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robert.foss@linaro.org, todor.too@gmail.com, mchehab@kernel.org, robh+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com, geert+renesas@glider.be, arnd@arndb.de, Anson.Huang@nxp.com, michael@walle.cc, agx@sigxcpu.org, max.oss.09@gmail.com, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno , Andrey Konovalov Subject: [PATCH v1 15/17] arm64: dts: sdm845: Add CAMSS ISP node Date: Fri, 8 Jan 2021 13:04:27 +0100 Message-Id: <20210108120429.895046-16-robert.foss@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210108120429.895046-1-robert.foss@linaro.org> References: <20210108120429.895046-1-robert.foss@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210108_070525_931578_3B254EAF X-CRM114-Status: GOOD ( 11.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Azam Sadiq Pasha Kapatrala Syed , Sarvesh Sridutt , Laurent Pinchart , Tomasz Figa Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the camss dt node for sdm845. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 151 +++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index bcf888381f14..286d50fcd9a5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3911,6 +3911,157 @@ videocc: clock-controller@ab00000 { #reset-cells = <1>; }; + camss: camss@a00000 { + compatible = "qcom,sdm845-camss"; + reg = <0 0xac65000 0 0x1000>, + <0 0xac66000 0 0x1000>, + <0 0xac67000 0 0x1000>, + <0 0xac68000 0 0x1000>, + <0 0xacb3000 0 0x1000>, + <0 0xacba000 0 0x1000>, + <0 0xacc8000 0 0x1000>, + <0 0xacaf000 0 0x4000>, + <0 0xacb6000 0 0x4000>, + <0 0xacc4000 0 0x4000>; + reg-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csid0", + "csid1", + "csid2", + "vfe0", + "vfe1", + "vfe_lite"; + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csid0", + "csid1", + "csid2", + "vfe0", + "vfe1", + "vfe_lite"; + power-domains = <&clock_camcc IFE_0_GDSC>, + <&clock_camcc IFE_1_GDSC>, + <&clock_camcc TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>; + clock-names = "gcc_camera_ahb", + "gcc_camera_axi", + "camnoc_axi", + "cpas_ahb", + "slow_ahb_src", + "soc_ahb", + "cphy_rx_src", + "csiphy0", + "csiphy0_timer_src", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer_src", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer_src", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer_src", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_src", + "vfe0_cphy_rx", + "csi0", /* renamed to fit naming-scheme of older hardware */ + "csi0_src", /* renamed to fit naming-scheme of older hardware */ + "vfe1_axi", + "vfe1", + "vfe1_src", + "vfe1_cphy_rx", + "csi1", /* renamed to fit naming-scheme of older hardware */ + "csi1_src", /* renamed to fit naming-scheme of older hardware */ + "vfe_lite", + "vfe_lite_src", + "vfe_lite_cphy_rx", + "csi2", /* renamed to fit naming-scheme of older hardware */ + "csi2_src"; /* renamed to fit naming-scheme of older hardware */ + + iommus = <&apps_smmu 0x0808 0x0>, + <&apps_smmu 0x0810 0x8>, + <&apps_smmu 0x0c08 0x0>, + <&apps_smmu 0x0c10 0x8>; + status = "disabled"; + + interconnects = + <&gladiator_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF0 + &mmss_noc SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF0_UNCOMP + &mmss_noc SLAVE_CAMNOC_UNCOMP>, + <&mmss_noc MASTER_CAMNOC_HF1 + &mmss_noc SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF1_UNCOMP + &mmss_noc SLAVE_CAMNOC_UNCOMP>, + <&mmss_noc MASTER_CAMNOC_SF + &mmss_noc SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_SF_UNCOMP + &mmss_noc SLAVE_CAMNOC_UNCOMP>; + interconnect-names = "cam_ahb", + "hf_1_mnoc", "hf_1_camnoc", + "hf_2_mnoc", "hf_2_camnoc", + "sf_1_mnoc", "sf_1_camnoc"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + cci: cci@ac4a000 { compatible = "qcom,sdm845-cci"; #address-cells = <1>;