| Message ID | 20210113180919.49523-1-linux@fw-web.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] dts64: mt7622: fix slow sd card access | expand |
On Wed, 2021-01-13 at 19:09 +0100, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Fix extreme slow speed (200MB takes ~20 min) on writing sdcard on > bananapi-r64 by adding reset-control for mmc1 like it's done for mmc0/emmc. > > Cc: stable@vger.kernel.org > Fixes: 2c002a3049f7 ("arm64: dts: mt7622: add mmc related device nodes") > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > --- > changes since v1: > - drop change to uhs-mode because mt7622 does not support it > --- > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > index 5b9ec032ce8d..7c6d871538a6 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > @@ -698,6 +698,8 @@ mmc1: mmc@11240000 { > clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, > <&topckgen CLK_TOP_AXI_SEL>; > clock-names = "source", "hclk"; > + resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>; > + reset-names = "hrst"; This looks ok to me. I think it's also necessary to trigger software reset for SD(mmc1) because loader(uboot) might mess up MSDC's registers. "Software reset" here will reset registers of AHB/AXI bus domain, such as MSDC_CFG[8:15]. msdc_reset_hw() in mtk-sd.c will only reset registers of MSDC CK domain.
On 13/01/2021 19:09, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > Fix extreme slow speed (200MB takes ~20 min) on writing sdcard on > bananapi-r64 by adding reset-control for mmc1 like it's done for mmc0/emmc. > > Cc: stable@vger.kernel.org > Fixes: 2c002a3049f7 ("arm64: dts: mt7622: add mmc related device nodes") > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Applied to v5.11-next/dts64 Thanks! > --- > changes since v1: > - drop change to uhs-mode because mt7622 does not support it > --- > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > index 5b9ec032ce8d..7c6d871538a6 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi > @@ -698,6 +698,8 @@ mmc1: mmc@11240000 { > clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, > <&topckgen CLK_TOP_AXI_SEL>; > clock-names = "source", "hclk"; > + resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>; > + reset-names = "hrst"; > status = "disabled"; > }; > >
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 5b9ec032ce8d..7c6d871538a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -698,6 +698,8 @@ mmc1: mmc@11240000 { clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, <&topckgen CLK_TOP_AXI_SEL>; clock-names = "source", "hclk"; + resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>; + reset-names = "hrst"; status = "disabled"; };