| Message ID | 20210114162432.3039657-3-steen.hegelund@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Adding the Sparx5 Switch Reset Driver | expand |
Hi, This commit is also missing a commit message and you could probably get some info from your cover letter here. On 14/01/2021 17:24:31+0100, Steen Hegelund wrote: > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> > --- > drivers/reset/Kconfig | 8 ++ > drivers/reset/Makefile | 1 + > drivers/reset/reset-microchip-sparx5.c | 120 +++++++++++++++++++++++++ > 3 files changed, 129 insertions(+) > create mode 100644 drivers/reset/reset-microchip-sparx5.c > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > index 71ab75a46491..05c240c47a8a 100644 > --- a/drivers/reset/Kconfig > +++ b/drivers/reset/Kconfig > @@ -101,6 +101,14 @@ config RESET_LPC18XX > help > This enables the reset controller driver for NXP LPC18xx/43xx SoCs. > > +config RESET_MCHP_SPARX5 > + bool "Microchip Sparx5 reset driver" > + depends on HAS_IOMEM || COMPILE_TEST > + default y if SPARX5_SWITCH > + select MFD_SYSCON > + help > + This driver supports switch core reset for the Microchip Sparx5 SoC. > + > config RESET_MESON > tristate "Meson Reset Driver" > depends on ARCH_MESON || COMPILE_TEST > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index 1054123fd187..341fd9ab4bf6 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o > obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o > obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o > obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o > +obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o > obj-$(CONFIG_RESET_MESON) += reset-meson.o > obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o > obj-$(CONFIG_RESET_NPCM) += reset-npcm.o > diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c > new file mode 100644 > index 000000000000..0dbd2b6161ef > --- /dev/null > +++ b/drivers/reset/reset-microchip-sparx5.c > @@ -0,0 +1,120 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* Microchip Sparx5 Switch Reset driver > + * > + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. > + * > + * The Sparx5 Chip Register Model can be browsed at this location: > + * https://github.com/microchip-ung/sparx-5_reginfo > + */ > +#include <linux/mfd/syscon.h> > +#include <linux/of_device.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > +#include <linux/reset-controller.h> > + > +#define PROTECT_REG 0x84 > +#define PROTECT_BIT BIT(10) > +#define SOFT_RESET_REG 0x08 > +#define SOFT_RESET_BIT BIT(1) > + > +struct mchp_reset_context { > + struct regmap *cpu_ctrl; > + struct regmap *gcb_ctrl; > + struct reset_controller_dev rcdev; > +}; > + > +static int sparx5_switch_reset(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct mchp_reset_context *ctx = > + container_of(rcdev, struct mchp_reset_context, rcdev); > + u32 val; > + I would ensure the reset only happens once here else I'm not sure how you could do it from the individual drivers. > + /* Make sure the core is PROTECTED from reset */ > + regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT); > + > + /* Start soft reset */ > + regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT); > + > + /* Wait for soft reset done */ > + return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val, > + (val & SOFT_RESET_BIT) == 0, > + 1, 100); > +} > +
On 19/01/2021 21:37:16+0100, Alexandre Belloni wrote: > On 14/01/2021 17:24:31+0100, Steen Hegelund wrote: > > +static int sparx5_switch_reset(struct reset_controller_dev *rcdev, > > + unsigned long id) > > +{ > > + struct mchp_reset_context *ctx = > > + container_of(rcdev, struct mchp_reset_context, rcdev); > > + u32 val; > > + > > I would ensure the reset only happens once here else I'm not sure how > you could do it from the individual drivers. > Ok, the core is taking care of that, nice.
Hi Alex, On Tue, 2021-01-19 at 21:37 +0100, Alexandre Belloni wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > Hi, > > This commit is also missing a commit message and you could probably > get > some info from your cover letter here. I will do that. > > On 14/01/2021 17:24:31+0100, Steen Hegelund wrote: > > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> > > --- > > drivers/reset/Kconfig | 8 ++ > > drivers/reset/Makefile | 1 + > > drivers/reset/reset-microchip-sparx5.c | 120 > > +++++++++++++++++++++++++ > > 3 files changed, 129 insertions(+) > > create mode 100644 drivers/reset/reset-microchip-sparx5.c > > > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > > index 71ab75a46491..05c240c47a8a 100644 > > --- a/drivers/reset/Kconfig > > +++ b/drivers/reset/Kconfig > > @@ -101,6 +101,14 @@ config RESET_LPC18XX > > help > > This enables the reset controller driver for NXP > > LPC18xx/43xx SoCs. > > > > +config RESET_MCHP_SPARX5 > > + bool "Microchip Sparx5 reset driver" > > + depends on HAS_IOMEM || COMPILE_TEST > > + default y if SPARX5_SWITCH > > + select MFD_SYSCON > > + help > > + This driver supports switch core reset for the Microchip > > Sparx5 SoC. > > + > > config RESET_MESON > > tristate "Meson Reset Driver" > > depends on ARCH_MESON || COMPILE_TEST > > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > > index 1054123fd187..341fd9ab4bf6 100644 > > --- a/drivers/reset/Makefile > > +++ b/drivers/reset/Makefile > > @@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o > > obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o > > obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o > > obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o > > +obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o > > obj-$(CONFIG_RESET_MESON) += reset-meson.o > > obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o > > obj-$(CONFIG_RESET_NPCM) += reset-npcm.o > > diff --git a/drivers/reset/reset-microchip-sparx5.c > > b/drivers/reset/reset-microchip-sparx5.c > > new file mode 100644 > > index 000000000000..0dbd2b6161ef > > --- /dev/null > > +++ b/drivers/reset/reset-microchip-sparx5.c > > @@ -0,0 +1,120 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* Microchip Sparx5 Switch Reset driver > > + * > > + * Copyright (c) 2020 Microchip Technology Inc. and its > > subsidiaries. > > + * > > + * The Sparx5 Chip Register Model can be browsed at this location: > > + * https://github.com/microchip-ung/sparx-5_reginfo > > + */ > > +#include <linux/mfd/syscon.h> > > +#include <linux/of_device.h> > > +#include <linux/module.h> > > +#include <linux/platform_device.h> > > +#include <linux/regmap.h> > > +#include <linux/reset-controller.h> > > + > > +#define PROTECT_REG 0x84 > > +#define PROTECT_BIT BIT(10) > > +#define SOFT_RESET_REG 0x08 > > +#define SOFT_RESET_BIT BIT(1) > > + > > +struct mchp_reset_context { > > + struct regmap *cpu_ctrl; > > + struct regmap *gcb_ctrl; > > + struct reset_controller_dev rcdev; > > +}; > > + > > +static int sparx5_switch_reset(struct reset_controller_dev *rcdev, > > + unsigned long id) > > +{ > > + struct mchp_reset_context *ctx = > > + container_of(rcdev, struct mchp_reset_context, > > rcdev); > > + u32 val; > > + > > I would ensure the reset only happens once here else I'm not sure how > you could do it from the individual drivers. The framework handles that automatically. > > > + /* Make sure the core is PROTECTED from reset */ > > + regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, > > PROTECT_BIT); > > + > > + /* Start soft reset */ > > + regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT); > > + > > + /* Wait for soft reset done */ > > + return regmap_read_poll_timeout(ctx->gcb_ctrl, > > SOFT_RESET_REG, val, > > + (val & SOFT_RESET_BIT) == 0, > > + 1, 100); > > +} > > + > > -- > Alexandre Belloni, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com Thanks for your comments BR Steen
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 71ab75a46491..05c240c47a8a 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -101,6 +101,14 @@ config RESET_LPC18XX help This enables the reset controller driver for NXP LPC18xx/43xx SoCs. +config RESET_MCHP_SPARX5 + bool "Microchip Sparx5 reset driver" + depends on HAS_IOMEM || COMPILE_TEST + default y if SPARX5_SWITCH + select MFD_SYSCON + help + This driver supports switch core reset for the Microchip Sparx5 SoC. + config RESET_MESON tristate "Meson Reset Driver" depends on ARCH_MESON || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 1054123fd187..341fd9ab4bf6 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o +obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c new file mode 100644 index 000000000000..0dbd2b6161ef --- /dev/null +++ b/drivers/reset/reset-microchip-sparx5.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Microchip Sparx5 Switch Reset driver + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * The Sparx5 Chip Register Model can be browsed at this location: + * https://github.com/microchip-ung/sparx-5_reginfo + */ +#include <linux/mfd/syscon.h> +#include <linux/of_device.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> + +#define PROTECT_REG 0x84 +#define PROTECT_BIT BIT(10) +#define SOFT_RESET_REG 0x08 +#define SOFT_RESET_BIT BIT(1) + +struct mchp_reset_context { + struct regmap *cpu_ctrl; + struct regmap *gcb_ctrl; + struct reset_controller_dev rcdev; +}; + +static int sparx5_switch_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mchp_reset_context *ctx = + container_of(rcdev, struct mchp_reset_context, rcdev); + u32 val; + + /* Make sure the core is PROTECTED from reset */ + regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT); + + /* Start soft reset */ + regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT); + + /* Wait for soft reset done */ + return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val, + (val & SOFT_RESET_BIT) == 0, + 1, 100); +} + +static const struct reset_control_ops sparx5_reset_ops = { + .reset = sparx5_switch_reset, +}; + +static int mchp_sparx5_reset_probe(struct platform_device *pdev) +{ + struct device_node *dn = pdev->dev.of_node; + struct regmap *cpu_ctrl, *gcb_ctrl; + struct device *dev = &pdev->dev; + struct mchp_reset_context *ctx; + struct device_node *syscon_np; + int err; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + syscon_np = of_parse_phandle(dn, "cpu-syscon", 0); + if (!syscon_np) + return -ENODEV; + cpu_ctrl = syscon_node_to_regmap(syscon_np); + of_node_put(syscon_np); + if (IS_ERR(cpu_ctrl)) { + err = PTR_ERR(cpu_ctrl); + dev_err(dev, "No cpu-syscon map: %d\n", err); + return err; + } + + syscon_np = of_parse_phandle(dn, "gcb-syscon", 0); + if (!syscon_np) + return -ENODEV; + gcb_ctrl = syscon_node_to_regmap(syscon_np); + of_node_put(syscon_np); + if (IS_ERR(gcb_ctrl)) { + err = PTR_ERR(gcb_ctrl); + dev_err(dev, "No gcb-syscon map: %d\n", err); + return err; + } + + ctx->cpu_ctrl = cpu_ctrl; + ctx->gcb_ctrl = gcb_ctrl; + + ctx->rcdev.owner = THIS_MODULE; + ctx->rcdev.nr_resets = 1; + ctx->rcdev.ops = &sparx5_reset_ops; + ctx->rcdev.of_node = dn; + + return devm_reset_controller_register(dev, &ctx->rcdev); +} + +static const struct of_device_id mchp_sparx5_reset_of_match[] = { + { + .compatible = "microchip,sparx5-switch-reset", + }, + { /*sentinel*/ } +}; + +static struct platform_driver mchp_sparx5_reset_driver = { + .probe = mchp_sparx5_reset_probe, + .driver = { + .name = "sparx5-switch-reset", + .of_match_table = mchp_sparx5_reset_of_match, + }, +}; + +static int __init mchp_sparx5_reset_init(void) +{ + return platform_driver_register(&mchp_sparx5_reset_driver); +} + +postcore_initcall(mchp_sparx5_reset_init); + +MODULE_DESCRIPTION("Microchip Sparx5 switch reset driver"); +MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>"); +MODULE_LICENSE("Dual MIT/GPL");
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> --- drivers/reset/Kconfig | 8 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-microchip-sparx5.c | 120 +++++++++++++++++++++++++ 3 files changed, 129 insertions(+) create mode 100644 drivers/reset/reset-microchip-sparx5.c