From patchwork Mon Jan 18 02:08:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 12026191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C462FC433E0 for ; Mon, 18 Jan 2021 02:11:28 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 882312251E for ; Mon, 18 Jan 2021 02:11:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 882312251E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=gJhnkBjTHPqh7eJbIujijce/d/3HfN3hztweg8sXrO0=; b=2MiuE6M2C4+r2qmXWxbe5hTveS 1WfD7StcA1yh4WfwUAYdnsp8ukRcfEX77Ydvq4/Qgk5tOMC0X1G5ZLycJI6fpYT3N3ell7NuFqGu/ UPwYpXMgWfMSa6LKwSwDa292pUxJYPeDFeDaobygUqrJFbInOu5FeH38oEou8/uRX38M6EE8FPdIj 0KQL5SPgdbecLmZdT6WHZczL2f9x3MpEwStodCjC16mGxH/yIP9Q+Y7khw7sVwoGPEA5QmcrNnOwf 6yxwLGBGjV1aUzdplkP99l28EXV+e8P/xoxQNjZ0GgpTzqEdIfrkGXdr68HkgaMzKZNKqs7obdKxm i5A8DCVg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l1JzM-0004nT-Gm; Mon, 18 Jan 2021 02:09:52 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l1Jz9-0004k5-CJ for linux-arm-kernel@lists.infradead.org; Mon, 18 Jan 2021 02:09:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6204011D4; Sun, 17 Jan 2021 18:09:38 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 634153F719; Sun, 17 Jan 2021 18:09:36 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v3 05/21] pinctrl: sunxi: Add support for the Allwinner H616-R pin controller Date: Mon, 18 Jan 2021 02:08:32 +0000 Message-Id: <20210118020848.11721-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210118020848.11721-1-andre.przywara@arm.com> References: <20210118020848.11721-1-andre.przywara@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210117_210939_581751_1E86DAD5 X-CRM114-Status: GOOD ( 17.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Samuel Holland , Yangtao Li , Linus Walleij , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, =?utf-8?b?Q2w=?= =?utf-8?b?w6ltZW50IFDDqXJvbg==?= , Shuosheng Huang , linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There are only two pins left now, used to connect to the PMIC via I2C. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Jernej Skrabec --- drivers/pinctrl/sunxi/Kconfig | 5 ++ drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c | 56 +++++++++++++++++++ 3 files changed, 62 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 73e88ce71a48..33751a6a0757 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -124,4 +124,9 @@ config PINCTRL_SUN50I_H616 default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN50I_H616_R + bool "Support for the Allwinner H616 R-PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 5359327a3c8f..d3440c42b9d6 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -24,5 +24,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o +obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c new file mode 100644 index 000000000000..8e4f10ab96ce --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner H616 R_PIO pin controller driver + * + * Copyright (C) 2020 Arm Ltd. + * Based on former work, which is: + * Copyright (C) 2017 Icenowy Zheng + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun50i_h616_r_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */ + SUNXI_FUNCTION(0x3, "s_i2c")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */ + SUNXI_FUNCTION(0x3, "s_i2c")), /* SDA */ +}; + +static const struct sunxi_pinctrl_desc sun50i_h616_r_pinctrl_data = { + .pins = sun50i_h616_r_pins, + .npins = ARRAY_SIZE(sun50i_h616_r_pins), + .pin_base = PL_BASE, +}; + +static int sun50i_h616_r_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun50i_h616_r_pinctrl_data); +} + +static const struct of_device_id sun50i_h616_r_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-h616-r-pinctrl", }, + {} +}; + +static struct platform_driver sun50i_h616_r_pinctrl_driver = { + .probe = sun50i_h616_r_pinctrl_probe, + .driver = { + .name = "sun50i-h616-r-pinctrl", + .of_match_table = sun50i_h616_r_pinctrl_match, + }, +}; +builtin_platform_driver(sun50i_h616_r_pinctrl_driver);