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Mon, 18 Jan 2021 00:50:44 -0500 (EST) From: Samuel Holland To: Thomas Gleixner , Marc Zyngier , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Subject: [PATCH v5 07/10] ARM: dts: sunxi: h3/h5: Add r_intc node Date: Sun, 17 Jan 2021 23:50:37 -0600 Message-Id: <20210118055040.21910-8-samuel@sholland.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210118055040.21910-1-samuel@sholland.org> References: <20210118055040.21910-1-samuel@sholland.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_005050_676510_2F705B2E X-CRM114-Status: GOOD ( 11.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Samuel Holland Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The H3 and H5 SoCs have an additional interrupt controller in the RTC power domain that can be used to enable wakeup for certain IRQs. Add a node for it. Acked-by: Maxime Ripard Signed-off-by: Samuel Holland --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 9be13378d4df..4bf25c5b873e 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -859,6 +859,15 @@ rtc: rtc@1f00000 { #clock-cells = <1>; }; + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun8i-h3-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f00c00 0x400>; + interrupts = ; + }; + r_ccu: clock@1f01400 { compatible = "allwinner,sun8i-h3-r-ccu"; reg = <0x01f01400 0x100>;