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Fri, 22 Jan 2021 11:51:30 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E0FC8100034; Fri, 22 Jan 2021 11:51:28 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D2C4D22DBCA; Fri, 22 Jan 2021 11:51:28 +0100 (CET) Received: from localhost (10.75.127.51) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 22 Jan 2021 11:51:28 +0100 From: To: Michael Turquette , Stephen Boyd , Rob Herring , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Etienne Carriere , Gabriel Fernandez Subject: [PATCH 14/14] ARM: dts: stm32: introduce basic boot include on stm32mp15x board Date: Fri, 22 Jan 2021 11:51:01 +0100 Message-ID: <20210122105101.27374-15-gabriel.fernandez@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210122105101.27374-1-gabriel.fernandez@foss.st.com> References: <20210122105101.27374-1-gabriel.fernandez@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-22_06:2021-01-21, 2021-01-22 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210122_055134_869324_5972BA45 X-CRM114-Status: GOOD ( 17.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Gabriel Fernandez Include this .dtsi file to be backward compatible with old basic bootchain. For example add: #include "stm32mp15-no-scmi.dtsi" in a stm32mp157c*.dts file. Signed-off-by: Gabriel Fernandez --- arch/arm/boot/dts/stm32mp15-no-scmi.dtsi | 158 +++++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp15-no-scmi.dtsi diff --git a/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi new file mode 100644 index 000000000000..4939f96da739 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15-no-scmi.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +/ { + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: clk-csi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + cpus { + cpu0: cpu@0 { + clocks = <&rcc CK_MPU>; + }; + + cpu1: cpu@1 { + clocks = <&rcc CK_MPU>; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&rcc>; + offset = <0x404>; + mask = <0x1>; + }; + + soc { + m_can1: can@4400e000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + + m_can2: can@4400f000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + + cryp1: cryp@54001000 { + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + }; + + dsi: dsi@5a000000 { + clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + }; + }; + + ahb { + m4_rproc: m4@10000000 { + resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; + + m4_system_resources { + m4_cec: cec@40016000 { + clocks = <&rcc CEC_K>, <&rcc CK_LSE>; + }; + + m4_m_can1: can@4400e000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + + m4_m_can2: can@4400f000 { + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + }; + }; + }; + }; + + firmware { + /delete-node/ scmi0; + /delete-node/ scmi1; + }; + /delete-node/ sram@2ffff000; +}; + +&cec { + clocks = <&rcc CEC_K>, <&clk_lse>; +}; + +&gpioz { + clocks = <&rcc GPIOZ>; +}; + +&hash1 { + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; +}; + +&i2c4 { + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; +}; + +&i2c6 { + clocks = <&rcc I2C6_K>; + resets = <&rcc I2C6_R>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; +}; + +&mdma1 { + clocks = <&rcc MDMA>; + resets = <&rcc MDMA_R>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc", "syscon"; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>; +}; + +&rng1 { + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; +}; + +&rtc { + clocks = <&rcc RTCAPB>, <&rcc RTC>; +}; + +&spi6 { + clocks = <&rcc SPI6_K>; + resets = <&rcc SPI6_R>; +}; + +&usart1 { + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; +};