diff mbox series

KVM: arm64: Correct spelling of DBGDIDR register

Message ID 20210128132823.35067-1-alexandru.elisei@arm.com (mailing list archive)
State New, archived
Headers show
Series KVM: arm64: Correct spelling of DBGDIDR register | expand

Commit Message

Alexandru Elisei Jan. 28, 2021, 1:28 p.m. UTC
The aarch32 debug ID register is called DBG*D*IDR (emphasis added), not
DBGIDR, use the correct spelling.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
---
Found while reviewing Marc's PMU and debug register fixes [1]. The patch
was created on top of that series and v5.11-rc3.

[1] https://lore.kernel.org/kvmarm/20210125122638.2947058-1-maz@kernel.org/

 arch/arm64/kvm/sys_regs.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Marc Zyngier Feb. 3, 2021, 11:01 a.m. UTC | #1
On Thu, 28 Jan 2021 13:28:23 +0000, Alexandru Elisei wrote:
> The aarch32 debug ID register is called DBG*D*IDR (emphasis added), not
> DBGIDR, use the correct spelling.

Applied to kvm-arm64/pmu-debug-fixes-5.11, thanks!

[1/1] KVM: arm64: Correct spelling of DBGDIDR register
      commit: 8c358b29e0dc69d5ced6acfea4cc3d1dcf10df27

Cheers,

	M.
diff mbox series

Patch

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 0434e1672810..56f08e9f48c6 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1714,7 +1714,7 @@  static const struct sys_reg_desc sys_reg_descs[] = {
 	{ SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
 };
 
-static bool trap_dbgidr(struct kvm_vcpu *vcpu,
+static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
 			struct sys_reg_params *p,
 			const struct sys_reg_desc *r)
 {
@@ -1761,8 +1761,8 @@  static bool trap_dbgidr(struct kvm_vcpu *vcpu,
  * guest. Revisit this one day, would this principle change.
  */
 static const struct sys_reg_desc cp14_regs[] = {
-	/* DBGIDR */
-	{ Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
+	/* DBGDIDR */
+	{ Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
 	/* DBGDTRRXext */
 	{ Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },