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bh=b0TEYyZ6Jpm1D9Hrf4Uirq5wkSl8rc4Igbimt+j818M=; b=s023ssOXW0VHUXvHkgnRj58NVY3VhDN46mnrnA8E6MrejdWjqEJzLPWpRQNaPY6I71 80ndr6F8frcEXDih6keyXQmxg7C2iyv1S32IGgYYrBS48qhOwjf/7m92KhSY8KIHFo9B hJtblOKr0GcwGUgZNGSvNy0X3qOW+mLryveKEipmNouTyZ1f1oP1fw5nVI1Cn2Zyth0S ml20izNdlG25cRm5qsQCoEPrHz8S3NA0dLXl55XNEIlt+BVXrKrvB3xQRfFVf853geTL QzA8Ma+LHDke0tXfv+oyVM8IuhgPVDTr5fHcUEsLz8/8x2SuFb4N3TlqRlpJpAUbNq1t eM+A== X-Gm-Message-State: AOAM53251Ms4mU+bJKzuaYO3ZNl3Okdrs/jUZWIf7fFQ7zCct3/NV8Ds nG0TQHxKywytTS4vvoHbTLk1hA== X-Google-Smtp-Source: ABdhPJw9Te6d20sslYeqPQX+ekmR/N9YluTXGvvWRjDjCRO5dsDJOKwTHO2iICQGBysLzgpFTvmQIg== X-Received: by 2002:a63:f95b:: with SMTP id q27mr16897164pgk.82.1612177492234; Mon, 01 Feb 2021 03:04:52 -0800 (PST) Received: from hsinyi-z840.tpe.corp.google.com ([2401:fa00:1:10:a0cd:1b84:6d56:68e1]) by smtp.gmail.com with ESMTPSA id i6sm18041057pgc.58.2021.02.01.03.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 03:04:51 -0800 (PST) From: Hsin-Yi Wang To: Matthias Brugger Subject: [PATCH] arm64: dts: mediatek: Add gce client reg for display subcomponents Date: Mon, 1 Feb 2021 19:04:47 +0800 Message-Id: <20210201110447.383473-1-hsinyi@chromium.org> X-Mailer: git-send-email 2.30.0.365.g02bc693789-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_060454_988791_CD2D5421 X-CRM114-Status: GOOD ( 11.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , linux-mediatek@lists.infradead.org, Enric Balletbo i Serra , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add mediatek,gce-client-reg for ccorr, aal, gamma, dither. Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183") Signed-off-by: Hsin-Yi Wang Tested-by: Enric Balletbo i Serra --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index b3b8afec5ab9a..0ed37dd9d80b4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1058,6 +1058,7 @@ ccorr0: ccorr@1400f000 { interrupts = ; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; aal0: aal@14010000 { @@ -1067,6 +1068,7 @@ aal0: aal@14010000 { interrupts = ; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; gamma0: gamma@14011000 { @@ -1075,6 +1077,7 @@ gamma0: gamma@14011000 { interrupts = ; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; dither0: dither@14012000 { @@ -1083,6 +1086,7 @@ dither0: dither@14012000 { interrupts = ; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; dsi0: dsi@14014000 {