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Tue, 02 Feb 2021 22:32:56 -0800 Received: from MTKMBS31N2.mediatek.inc (172.27.4.87) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 2 Feb 2021 22:32:53 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 3 Feb 2021 14:32:46 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 3 Feb 2021 14:32:46 +0800 From: Chunfeng Yun To: Rob Herring , Matthias Brugger , Mathias Nyman Subject: [RFC PATCH 3/3] arm64: dts: mt8195: add USB related nodes Date: Wed, 3 Feb 2021 14:31:59 +0800 Message-ID: <20210203063159.11021-3-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210203063159.11021-1-chunfeng.yun@mediatek.com> References: <20210203063159.11021-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: B788B26AA748834F35E1F108DA8F78F6660A6C51C78035BFD44E6544A033CAD72000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210203_013304_758135_F6D1C9EE X-CRM114-Status: GOOD ( 15.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Nicolas Boichat , Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Chunfeng Yun , Ikjoon Jang , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add USB nodes, PHY nodes and some fixed regulator nodes. We prefer to use mt8192's compatible for the first USB controller (port0), there is no wrong with the SOF/ITP interval; but for other controllers (port1~port3) should use mt8195's one due to the wrong default setting of SOF/ITP interval which should be calculated from 48M, but not 24M by default. Signed-off-by: Chunfeng Yun --- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 70 +++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 163 ++++++++++++++++++++ 2 files changed, 233 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index 7264232bb7e9..a60682752e19 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "mt8195.dtsi" #include "mt6359.dtsi" +#include / { model = "MediaTek MT8195 evaluation board"; @@ -49,6 +50,36 @@ enable-active-high; regulator-always-on; }; + + usb_p0_vbus: regulator@2 { + compatible = "regulator-fixed"; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; + + usb_p2_vbus: regulator@3 { + compatible = "regulator-fixed"; + gpio = <&pio 131 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; + + usb_p3_vbus: regulator@4 { + compatible = "regulator-fixed"; + gpio = <&pio 5 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; }; &pmic { @@ -156,6 +187,22 @@ status = "okay"; }; +&u3phy0 { + status="okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status="okay"; +}; + +&u3phy3 { + status="okay"; +}; + &pio { nor_pins_default: nordefault { pins0 { @@ -311,3 +358,26 @@ }; }; + +&xhci0 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_p0_vbus>; + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_p2_vbus>; + status = "okay"; +}; + +&xhci3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_p3_vbus>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index ccb9d24b1c1e..60c75b23cf03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -914,6 +915,83 @@ status = "disabled"; }; + xhci0: usb@11200000 { + compatible = "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>, + <&topckgen CLK_TOP_SSUSB_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + + xhci1: usb@11290000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11290000 0 0x1000>, + <0 0x11293e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_1P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_1P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P1_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + + xhci2: usb@112a0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112a0000 0 0x1000>, + <0 0x112a3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port2 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_2P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_2P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P2_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + + xhci3: usb@112b0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port3 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_3P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_3P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P3_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + pcie0: pcie@112f0000 { device_type = "pci"; compatible = "mediatek,mt8195-pcie"; @@ -998,6 +1076,40 @@ status = "disabled"; }; + u3phy2: usb-phy2@11c40000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c40000 0x700>; + status = "disabled"; + + u2port2: usb2-phy2@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + u3phy3: usb-phy3@11c50000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x700>; + status = "disabled"; + + u2port3: usb2-phy3@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + i2c5: i2c5@11d00000 { compatible = "mediatek,mt8195-i2c", "mediatek,mt8192-i2c"; @@ -1138,6 +1250,57 @@ #clock-cells = <1>; }; + u3phy1: usb-phy1@11e30000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e30000 0x1000>; + status = "disabled"; + + u2port1: usb2-phy1@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb3-phy1@700 { + reg = <0x700 0x900>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + u3phy0: usb-phy0@11e40000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e40000 0x1000>; + status = "disabled"; + + u2port0: usb2-phy0@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb3-phy0@700 { + reg = <0x700 0 0x900>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + pciephy: phy@11e80000 { compatible = "mediatek,mt8195-pcie-phy"; #address-cells = <2>;