diff mbox series

[RFC,v2,1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195

Message ID 20210203102642.7353-1-chunfeng.yun@mediatek.com (mailing list archive)
State New, archived
Headers show
Series [RFC,v2,1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195 | expand

Commit Message

Chunfeng Yun Feb. 3, 2021, 10:26 a.m. UTC
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz. Here add a new compatible
for MT8195, it's also supported in driver. But the first controller
(IP0) has no such issue, we prefer to use generic compatible,
e.g. mt8192's compatible.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 +
 1 file changed, 1 insertion(+)

Comments

Greg Kroah-Hartman Feb. 3, 2021, 10:31 a.m. UTC | #1
On Wed, Feb 03, 2021 at 06:26:40PM +0800, Chunfeng Yun wrote:
> There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> exclude IP0) have a wrong default SOF/ITP interval which is
> calculated from the frame counter clock 24Mhz by default, but
> in fact, the frame counter clock is 48Mhz, so we should set
> the accurate interval according to 48Mhz. Here add a new compatible
> for MT8195, it's also supported in driver. But the first controller
> (IP0) has no such issue, we prefer to use generic compatible,
> e.g. mt8192's compatible.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: no changes

Note, I do not apply patches with "RFC" as obviously you do not think
they are worthy of being applied.  I don't see what you are asking to be
done with this set of patches, please explain?

thanks,

greg k-h
Greg Kroah-Hartman Feb. 5, 2021, 9:09 a.m. UTC | #2
On Wed, Feb 03, 2021 at 06:26:40PM +0800, Chunfeng Yun wrote:
> There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> exclude IP0) have a wrong default SOF/ITP interval which is
> calculated from the frame counter clock 24Mhz by default, but
> in fact, the frame counter clock is 48Mhz, so we should set
> the accurate interval according to 48Mhz. Here add a new compatible
> for MT8195, it's also supported in driver. But the first controller
> (IP0) has no such issue, we prefer to use generic compatible,
> e.g. mt8192's compatible.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: no changes

Note, I do not apply patches that have "RFC" as that means you do not
feel comfortable with them being applied.

Please resend without that when you feel they are ready to be merged.

thanks,

greg k-h
Chunfeng Yun Feb. 7, 2021, 2:10 a.m. UTC | #3
On Wed, 2021-02-03 at 11:31 +0100, Greg Kroah-Hartman wrote:
> On Wed, Feb 03, 2021 at 06:26:40PM +0800, Chunfeng Yun wrote:
> > There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> > exclude IP0) have a wrong default SOF/ITP interval which is
> > calculated from the frame counter clock 24Mhz by default, but
> > in fact, the frame counter clock is 48Mhz, so we should set
> > the accurate interval according to 48Mhz. Here add a new compatible
> > for MT8195, it's also supported in driver. But the first controller
> > (IP0) has no such issue, we prefer to use generic compatible,
> > e.g. mt8192's compatible.
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > v2: no changes
> 
> Note, I do not apply patches with "RFC" as obviously you do not think
> they are worthy of being applied.  I don't see what you are asking to be
> done with this set of patches, please explain?
The DTS patch [2/3] in the series will cause merge conflict, due to the
dependent patches are not upstreamed.

Another problem is that I wander to know whether the compatible usage as
following is allowed:

arch/arm64/boot/dts/mediatek/mt8195.dtsi

   usb@11200000 {  // ip0
        compatible = "mediatek,mt8192-xhci",  // here use mt8192's
compatible, avoid changing SOF/ITP interval for ip0, because it's
default value is ok."mediatek,mt8192-xhci" is not supported in driver,
so finally will use generic copatible "mediatek,mtk-xhci".

                     "mediatek,mtk-xhci";
        ....
    };

   usb@11290000 {  // ip1
        compatible = "mediatek,mt8195-xhci",  // here use mt8195's
compatible, used to change SOF/ITP interval, due the the wrong default
value.
                     "mediatek,mtk-xhci";
   };

   usb@112a0000 {  // ip2
        compatible = "mediatek,mt8195-xhci",  // same as ip1
                     "mediatek,mtk-xhci";
    };

Thank you

> 
> thanks,
> 
> greg k-h
Rob Herring Feb. 10, 2021, 9:58 p.m. UTC | #4
On Wed, 03 Feb 2021 18:26:40 +0800, Chunfeng Yun wrote:
> There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> exclude IP0) have a wrong default SOF/ITP interval which is
> calculated from the frame counter clock 24Mhz by default, but
> in fact, the frame counter clock is 48Mhz, so we should set
> the accurate interval according to 48Mhz. Here add a new compatible
> for MT8195, it's also supported in driver. But the first controller
> (IP0) has no such issue, we prefer to use generic compatible,
> e.g. mt8192's compatible.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: no changes
> ---
>  Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
index 42d8814f903a..02cba4212f7d 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
@@ -16,6 +16,7 @@  Required properties:
 	"mediatek,mtk-xhci" compatible string, you need SoC specific ones in
 	addition, one of:
 	- "mediatek,mt8173-xhci"
+	- "mediatek,mt8195-xhci"
  - reg : specifies physical base address and size of the registers
  - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
  - interrupts : interrupt used by the controller