| Message ID | 20210203133138.10754-3-kostap@marvell.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Device tree fixes for Armada family | expand |
Hi Konstantin, On Wed, Feb 03 2021, kostap@marvell.com wrote: > From: Konstantin Porotchkin <kostap@marvell.com> > > Update the settings for AP806 SDHCI interface according to > latest Xenon drivers changes. > - no need to select the PHY slow mode anymore Why? Has anything changed since the introduction of marvell,xenon-phy-slow-mode? baruch > - recommended to add HS400 support at 1.8V signalling on AP806-B0 > - fix the bus witdth for A8040 DB from 4 to 8 bits. > > Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> > --- > arch/arm64/boot/dts/marvell/armada-8040-db.dts | 11 ++++++++++- > arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 5 ----- > arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 1 - > 3 files changed, 10 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts > index 09fb5256f1db..6362e654a823 100644 > --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts > +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts > @@ -347,7 +347,16 @@ > > &ap_sdhci0 { > status = "okay"; > - bus-width = <4>; > + bus-width = <8>; > + /* The below property should be added to boards with AP806-B0 > + * for enabling HS400 speed mode. Otherwise the device highest > + * speed mode will be HS200. > + * Should not be added to boards with earlier release of AP806 > + * since it will cause SDHCI driver to fail upon initialization. > + * Reference - HWE-7296210 (errata for releases A0/A1/A2) > + * > + * mmc-hs400-1_8v; > + */ > non-removable; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi > index 73733b4126e2..69653de998e2 100644 > --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi > @@ -109,11 +109,6 @@ > > &ap_sdhci0 { > bus-width = <8>; > - /* > - * Not stable in HS modes - phy needs "more calibration", so add > - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. > - */ > - marvell,xenon-phy-slow-mode; > no-1-8-v; > no-sd; > no-sdio; > diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > index 12e477f1aeb9..edd6131a0587 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > @@ -257,7 +257,6 @@ > clock-names = "core"; > clocks = <&ap_clk 4>; > dma-coherent; > - marvell,xenon-phy-slow-mode; > status = "disabled"; > };
Hi, Baruch, > -----Original Message----- > From: Baruch Siach <baruch@tkos.co.il> > Sent: Wednesday, February 3, 2021 15:59 > To: Kostya Porotchkin <kostap@marvell.com> > Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; > andrew@lunn.ch; jaz@semihalf.com; gregory.clement@bootlin.com; > linux@armlinux.org.uk; Nadav Haklai <nadavh@marvell.com>; > robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>; > mw@semihalf.com; Ben Peled <bpeled@marvell.com>; > sebastian.hesselbarth@gmail.com; linux-arm-kernel@lists.infradead.org > Subject: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI > settings > > External Email > > ---------------------------------------------------------------------- > Hi Konstantin, > > On Wed, Feb 03 2021, kostap@marvell.com wrote: > > From: Konstantin Porotchkin <kostap@marvell.com> > > > > Update the settings for AP806 SDHCI interface according to latest > > Xenon drivers changes. > > - no need to select the PHY slow mode anymore > > Why? Has anything changed since the introduction of marvell,xenon-phy-slow- > mode? [KP] AP806 B0, AP807 and later do not need the "slow mode" set by the default. The HWE-7296210 errata is not applicable to these components and they are able to run AP SDHCI in HS400 8-bit mode. Kosta > > baruch > > > - * Not stable in HS modes - phy needs "more calibration", so add > > - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. > > - */ > > - marvell,xenon-phy-slow-mode; > > no-1-8-v; > > no-sd; > > no-sdio; > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > > b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > > index 12e477f1aeb9..edd6131a0587 100644 > > --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > > +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi > > @@ -257,7 +257,6 @@ > > clock-names = "core"; > > clocks = <&ap_clk 4>; > > dma-coherent; > > - marvell,xenon-phy-slow-mode; > > status = "disabled"; > > }; > > > -- > ~. .~ Tk Open Systems > =}------------------------------------------------ooO--U--Ooo------------{= > - baruch@tkos.co.il - tel: +972.52.368.4656, > https://urldefense.proofpoint.com/v2/url?u=http- > 3A__www.tkos.co.il&d=DwIBAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=- > N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=F567knLB6kbyr- > BZRqLFLJgXHENu41578OHxsKQQ- > sw&s=eXEBLtBC3CwWIF9XFbHrgSgASz4aMgHi5W1uuXTgdQ4&e= -
On Wed, Feb 03, 2021 at 02:37:22PM +0000, Kostya Porotchkin wrote: > Hi, Baruch, > > > -----Original Message----- > > From: Baruch Siach <baruch@tkos.co.il> > > Sent: Wednesday, February 3, 2021 15:59 > > To: Kostya Porotchkin <kostap@marvell.com> > > Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; > > andrew@lunn.ch; jaz@semihalf.com; gregory.clement@bootlin.com; > > linux@armlinux.org.uk; Nadav Haklai <nadavh@marvell.com>; > > robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>; > > mw@semihalf.com; Ben Peled <bpeled@marvell.com>; > > sebastian.hesselbarth@gmail.com; linux-arm-kernel@lists.infradead.org > > Subject: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI > > settings > > > > External Email > > > > ---------------------------------------------------------------------- > > Hi Konstantin, > > > > On Wed, Feb 03 2021, kostap@marvell.com wrote: > > > From: Konstantin Porotchkin <kostap@marvell.com> > > > > > > Update the settings for AP806 SDHCI interface according to latest > > > Xenon drivers changes. > > > - no need to select the PHY slow mode anymore > > > > Why? Has anything changed since the introduction of marvell,xenon-phy-slow- > > mode? > [KP] AP806 B0, AP807 and later do not need the "slow mode" set by the default. > The HWE-7296210 errata is not applicable to these components and they are able > to run AP SDHCI in HS400 8-bit mode. So what about all those people, such as me, who have A0 silicon on their Macchiatobin boards? You can't just go around removing DT properties like this.
> -----Original Message----- > From: Russell King - ARM Linux admin <linux@armlinux.org.uk> > Sent: Wednesday, February 3, 2021 16:39 > To: Kostya Porotchkin <kostap@marvell.com> > Cc: Baruch Siach <baruch@tkos.co.il>; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; andrew@lunn.ch; jaz@semihalf.com; > gregory.clement@bootlin.com; Nadav Haklai <nadavh@marvell.com>; > robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>; > mw@semihalf.com; Ben Peled <bpeled@marvell.com>; > sebastian.hesselbarth@gmail.com; linux-arm-kernel@lists.infradead.org > Subject: Re: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI > settings > > On Wed, Feb 03, 2021 at 02:37:22PM +0000, Kostya Porotchkin wrote: > > Hi, Baruch, > > > > > -----Original Message----- > > > From: Baruch Siach <baruch@tkos.co.il> > > > Sent: Wednesday, February 3, 2021 15:59 > > > To: Kostya Porotchkin <kostap@marvell.com> > > > Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; > > > andrew@lunn.ch; jaz@semihalf.com; gregory.clement@bootlin.com; > > > linux@armlinux.org.uk; Nadav Haklai <nadavh@marvell.com>; > > > robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>; > > > mw@semihalf.com; Ben Peled <bpeled@marvell.com>; > > > sebastian.hesselbarth@gmail.com; > > > linux-arm-kernel@lists.infradead.org > > > Subject: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI > > > settings > > > > > > External Email > > > > > > -------------------------------------------------------------------- > > > -- > > > Hi Konstantin, > > > > > > On Wed, Feb 03 2021, kostap@marvell.com wrote: > > > > From: Konstantin Porotchkin <kostap@marvell.com> > > > > > > > > Update the settings for AP806 SDHCI interface according to latest > > > > Xenon drivers changes. > > > > - no need to select the PHY slow mode anymore > > > > > > Why? Has anything changed since the introduction of > > > marvell,xenon-phy-slow- mode? > > [KP] AP806 B0, AP807 and later do not need the "slow mode" set by the > default. > > The HWE-7296210 errata is not applicable to these components and they > > are able to run AP SDHCI in HS400 8-bit mode. > > So what about all those people, such as me, who have A0 silicon on their > Macchiatobin boards? > > You can't just go around removing DT properties like this. > [KP] So for older systems this "slow mode" parameter could be set on the board level. When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR52, even if they support HS400 on AP side. MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v" flag set, so it should remain in low speed anyway. > -- > RMK's Patch system: https://urldefense.proofpoint.com/v2/url?u=https- > 3A__www.armlinux.org.uk_developer_patches_&d=DwIBAg&c=nKjWec2b6R0 > mOyPaz7xtfQ&r=- > N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=yMC9YPQXZUm > QPwlD7KCTVoVTPXCTQwTXD2yVsAo6sxA&s=OuBO2QArzHvV4k_vsNZdmSoDX > rL4Q_voTqxrlYU6KKE&e= > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
> -----Original Message----- > From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org> On > Behalf Of Kostya Porotchkin > Sent: Wednesday, February 3, 2021 16:51 > To: Russell King - ARM Linux admin <linux@armlinux.org.uk> > Cc: devicetree@vger.kernel.org; Baruch Siach <baruch@tkos.co.il>; > andrew@lunn.ch; jaz@semihalf.com; gregory.clement@bootlin.com; linux- > kernel@vger.kernel.org; Nadav Haklai <nadavh@marvell.com>; > robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>; > mw@semihalf.com; Ben Peled <bpeled@marvell.com>; linux-arm- > kernel@lists.infradead.org; sebastian.hesselbarth@gmail.com > Subject: RE: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI > settings [KP] > > > > Hi Konstantin, > > > > > > > > On Wed, Feb 03 2021, kostap@marvell.com wrote: > > > > > From: Konstantin Porotchkin <kostap@marvell.com> > > > > > > > > > > Update the settings for AP806 SDHCI interface according to > > > > > latest Xenon drivers changes. > > > > > - no need to select the PHY slow mode anymore > > > > > > > > Why? Has anything changed since the introduction of > > > > marvell,xenon-phy-slow- mode? > > > [KP] AP806 B0, AP807 and later do not need the "slow mode" set by > > > the > > default. > > > The HWE-7296210 errata is not applicable to these components and > > > they are able to run AP SDHCI in HS400 8-bit mode. > > > > So what about all those people, such as me, who have A0 silicon on > > their Macchiatobin boards? > > > > You can't just go around removing DT properties like this. > > > [KP] So for older systems this "slow mode" parameter could be set on the > board level. > When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR52, even if > they support HS400 on AP side. > MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v" flag > set, so it should remain in low speed anyway. [KP] I also forgot to mention this code piece in Xenon driver: /* Disable HS200 on Armada AP806 */ if (priv->hw_version == XENON_AP806) host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; > > > -- > > RMK's Patch system: https://urldefense.proofpoint.com/v2/url?u=https- > > > 3A__www.armlinux.org.uk_developer_patches_&d=DwIBAg&c=nKjWec2b6R0 > > mOyPaz7xtfQ&r=- > > > N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=yMC9YPQXZUm > > > QPwlD7KCTVoVTPXCTQwTXD2yVsAo6sxA&s=OuBO2QArzHvV4k_vsNZdmSoDX > > rL4Q_voTqxrlYU6KKE&e= > > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last! > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > https://urldefense.proofpoint.com/v2/url?u=http- > 3A__lists.infradead.org_mailman_listinfo_linux-2Darm- > 2Dkernel&d=DwICAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=- > N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=8f- > 1fnISJVHCS4gZTeFgRPXGPiwBevUsFbmYDBmkRWM&s=RBlEEUXG0sOmZHsQ > Omurf018V8kSE_IMZR7bDLVJ0FA&e=
On Wed, Feb 03, 2021 at 02:50:45PM +0000, Kostya Porotchkin wrote: > [KP] So for older systems this "slow mode" parameter could be set on the board level. > When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR52, even if they support HS400 on AP side. > MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v" flag set, so it should remain in low speed anyway. Your reasoning does not make sense. The ap80x.dtsi file does not specify "marvell,xenon-phy-slow-mode". It is not specified at this level. It is already specified at board level. Given that Macchiatobin will still use slow mode, why remove the marvell,xenon-phy-slow-mode property from this file? Also, if you're upgrading ap80x.dtsi to use a bus-width of 8, why keep the bus-width specifier of 8 in the board files? This patch just doesn't make sense, and your responses to our points seem to add to the confusion.
Hello, Russell, I agree that this patch needs rework. I will definitely do it and issue a new version. > On Wed, Feb 03, 2021 at 02:50:45PM +0000, Kostya Porotchkin wrote: > > [KP] So for older systems this "slow mode" parameter could be set on the > board level. > > When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR52, even > if they support HS400 on AP side. > > MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v" > flag set, so it should remain in low speed anyway. > > Your reasoning does not make sense. > > The ap80x.dtsi file does not specify "marvell,xenon-phy-slow-mode". > It is not specified at this level. It is already specified at board level. [KP] it does. In current armada-ap80x.dtsi File this specification is on row 260: ap_sdhci0: sdhci@6e0000 { compatible = "marvell,armada-ap806-sdhci"; reg = <0x6e0000 0x300>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clock-names = "core"; clocks = <&ap_clk 4>; dma-coherent; marvell,xenon-phy-slow-mode; status = "disabled"; }; So I would like to remove this row. > Given that Macchiatobin will still use slow mode, why remove the > marvell,xenon-phy-slow-mode property from this file? [KP] Agree, I will keep this property in Macchiatobin DTS file. > > Also, if you're upgrading ap80x.dtsi to use a bus-width of 8, why keep the bus- > width specifier of 8 in the board files? [KP] The bus width is updated in A8040 DB DTS. This board utilizes 8-bit interface. The armada-ap80x.dtsi file does not specifies the bus width since it is board-specific. > > This patch just doesn't make sense, and your responses to our points seem to > add to the confusion. [KP] I am sorry about it. Hope my last response clarifies it. Kosta > > -- > RMK's Patch system: https://urldefense.proofpoint.com/v2/url?u=https- > 3A__www.armlinux.org.uk_developer_patches_&d=DwIBAg&c=nKjWec2b6R0 > mOyPaz7xtfQ&r=- > N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=V27OOcgNqKN2 > WrlW2YFvHm_D_dXoP44wPd5zyOKvEBk&s=o3OrmStt1ZuXVNlYklTV_b1wY35 > NvPPrdLqwGgtxRZU&e= > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
Hi Kosta, Let me chime in. śr., 3 lut 2021 o 17:57 Kostya Porotchkin <kostap@marvell.com> napisał(a): > > Hello, Russell, > I agree that this patch needs rework. > I will definitely do it and issue a new version. > > > On Wed, Feb 03, 2021 at 02:50:45PM +0000, Kostya Porotchkin wrote: > > > [KP] So for older systems this "slow mode" parameter could be set on the > > board level. > > > When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR52, even > > if they support HS400 on AP side. > > > MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v" > > flag set, so it should remain in low speed anyway. > > > > Your reasoning does not make sense. > > > > The ap80x.dtsi file does not specify "marvell,xenon-phy-slow-mode". > > It is not specified at this level. It is already specified at board level. > [KP] it does. In current armada-ap80x.dtsi File this specification is on row 260: > ap_sdhci0: sdhci@6e0000 { > compatible = "marvell,armada-ap806-sdhci"; > reg = <0x6e0000 0x300>; > interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "core"; > clocks = <&ap_clk 4>; > dma-coherent; > marvell,xenon-phy-slow-mode; > status = "disabled"; > }; > So I would like to remove this row. > > > Given that Macchiatobin will still use slow mode, why remove the > > marvell,xenon-phy-slow-mode property from this file? > [KP] Agree, I will keep this property in Macchiatobin DTS file. > Please do it another way around. 1. We need to leave the device tree bindings intact as much as possible - specifically for Armada 7k8k changes in this area have been causing enough problems in the past, breaking compatibility between kernel revisions. Moving the property to board level can be good here, but forces all other board dts files to adjust. Unfortunately Linux is a source of truth for the arm64 device tree bindings, but please note other OS's use those files as well - let's minimize the impact for existing HW and drivers. 2. What I propose is to remove `marvell,xenon-phy-slow-mode` from armada-ap80x.dtsi and add below in armada-ap806.dtsi: &ap_sdhci0 { marvell,xenon-phy-slow-mode; }; This way AP807 becomes free from the unwanted slow mode setting. Also any user of Armada 7k8k the B0 revision can add below to the board file: &ap_sdhci0 { + /delete-property/marvell,xenon-phy-slow-mode; }; 3. Contrary to the SDK version, sdhci-xenon.c is not capable of checking the SoC revision. HS200 is disabled for all versions of AP806 there - I believe this place requires revisiting, to start relying explicitly on the `marvell,xenon-phy-slow-mode` setting, rather than the compatible string. I can handle this one. 4. Please move armada-8040-db.dts changes to a separate patch, please. Thanks, Marcin > > > > Also, if you're upgrading ap80x.dtsi to use a bus-width of 8, why keep the bus- > > width specifier of 8 in the board files? > [KP] The bus width is updated in A8040 DB DTS. This board utilizes 8-bit interface. > The armada-ap80x.dtsi file does not specifies the bus width since it is board-specific. > > > > > This patch just doesn't make sense, and your responses to our points seem to > > add to the confusion. > [KP] I am sorry about it. Hope my last response clarifies it. > > Kosta > > > > -- > > RMK's Patch system: https://urldefense.proofpoint.com/v2/url?u=https- > > 3A__www.armlinux.org.uk_developer_patches_&d=DwIBAg&c=nKjWec2b6R0 > > mOyPaz7xtfQ&r=- > > N9sN4p5NSr0JGQoQ_2UCOgAqajG99W1EbSOww0WU8o&m=V27OOcgNqKN2 > > WrlW2YFvHm_D_dXoP44wPd5zyOKvEBk&s=o3OrmStt1ZuXVNlYklTV_b1wY35 > > NvPPrdLqwGgtxRZU&e= > > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 09fb5256f1db..6362e654a823 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -347,7 +347,16 @@ &ap_sdhci0 { status = "okay"; - bus-width = <4>; + bus-width = <8>; + /* The below property should be added to boards with AP806-B0 + * for enabling HS400 speed mode. Otherwise the device highest + * speed mode will be HS200. + * Should not be added to boards with earlier release of AP806 + * since it will cause SDHCI driver to fail upon initialization. + * Reference - HWE-7296210 (errata for releases A0/A1/A2) + * + * mmc-hs400-1_8v; + */ non-removable; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index 73733b4126e2..69653de998e2 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -109,11 +109,6 @@ &ap_sdhci0 { bus-width = <8>; - /* - * Not stable in HS modes - phy needs "more calibration", so add - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. - */ - marvell,xenon-phy-slow-mode; no-1-8-v; no-sd; no-sdio; diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index 12e477f1aeb9..edd6131a0587 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -257,7 +257,6 @@ clock-names = "core"; clocks = <&ap_clk 4>; dma-coherent; - marvell,xenon-phy-slow-mode; status = "disabled"; };