| Message ID | 20210226103028.729172-4-t.schramm@manjaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add i2s support for sun8i V3 and S3 SoCs | expand |
Hi, On Fri, Feb 26, 2021 at 11:30:28AM +0100, Tobias Schramm wrote: > The V3 and S3 SoCs feature an i2s peripheral identical to that of the H3. > Add it to the dts. > > Signed-off-by: Tobias Schramm <t.schramm@manjaro.org> Why is it added to the v3 DTSI and not the global one? > --- > arch/arm/boot/dts/sun8i-v3.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi > index c279e13583ba..17ea6b8f091f 100644 > --- a/arch/arm/boot/dts/sun8i-v3.dtsi > +++ b/arch/arm/boot/dts/sun8i-v3.dtsi > @@ -30,3 +30,18 @@ uart1_pg_pins: uart1-pg-pins { > function = "uart1"; > }; > }; > + > +&soc { You don't need a label for that, you can just put it under / { soc { > + i2s0: i2s@1c22000 { > + #sound-dai-cells = <0>; > + compatible = "allwinner,sun8i-h3-i2s"; We should also have a v3 specific compatible here in addition to the H3 (and document it in the bindings). Maxime
diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi index c279e13583ba..17ea6b8f091f 100644 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -30,3 +30,18 @@ uart1_pg_pins: uart1-pg-pins { function = "uart1"; }; }; + +&soc { + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-i2s"; + reg = <0x01c22000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_I2S0>; + status = "disabled"; + }; +};
The V3 and S3 SoCs feature an i2s peripheral identical to that of the H3. Add it to the dts. Signed-off-by: Tobias Schramm <t.schramm@manjaro.org> --- arch/arm/boot/dts/sun8i-v3.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)