| Message ID | 20210302102846.619980-2-claudiu.beznea@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | irqchip/mchp-eic: add driver for Microchip EIC | expand |
On Tue, 02 Mar 2021 10:28:45 +0000, Claudiu Beznea <claudiu.beznea@microchip.com> wrote: > > Add DT bindings for Microchip External Interrupt Controller. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > .../interrupt-controller/mchp,eic.yaml | 74 +++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml > new file mode 100644 > index 000000000000..5a927817aa7d > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/mchp,eic.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip External Interrupt Controller > + > +maintainers: > + - Claudiu Beznea <claudiu.beznea@microchip.com> > + > +description: > + This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides > + support for handling up to 2 external interrupt lines. > + > +properties: > + compatible: > + enum: > + - microchip,sama7g5-eic > + > + reg: > + maxItems: 1 > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 3 > + description: > + The first cell is the input IRQ number (between 0 and 1), the second cell > + is the trigger type as defined in interrupt.txt present in this directory > + and the third cell is the glitch filter (1, 2, 4, 8) in clock cycles This last parameter looks like a very bad idea. How do you plan for that to be used? Which clock cycles? In any case, I don't think it should be part of the interrupt descriptor, but provided as a static configuration at the interrupt controller level itself. Thanks, M.
On 02.03.2021 13:32, Marc Zyngier wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Tue, 02 Mar 2021 10:28:45 +0000, > Claudiu Beznea <claudiu.beznea@microchip.com> wrote: >> >> Add DT bindings for Microchip External Interrupt Controller. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> >> --- >> .../interrupt-controller/mchp,eic.yaml | 74 +++++++++++++++++++ >> 1 file changed, 74 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml >> new file mode 100644 >> index 000000000000..5a927817aa7d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml >> @@ -0,0 +1,74 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/interrupt-controller/mchp,eic.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Microchip External Interrupt Controller >> + >> +maintainers: >> + - Claudiu Beznea <claudiu.beznea@microchip.com> >> + >> +description: >> + This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides >> + support for handling up to 2 external interrupt lines. >> + >> +properties: >> + compatible: >> + enum: >> + - microchip,sama7g5-eic >> + >> + reg: >> + maxItems: 1 >> + >> + interrupt-controller: true >> + >> + '#interrupt-cells': >> + const: 3 >> + description: >> + The first cell is the input IRQ number (between 0 and 1), the second cell >> + is the trigger type as defined in interrupt.txt present in this directory >> + and the third cell is the glitch filter (1, 2, 4, 8) in clock cycles > > This last parameter looks like a very bad idea. How do you plan for > that to be used? Which clock cycles? I was in balance weter I should add this parameter here or not. I will remove it. > > In any case, I don't think it should be part of the interrupt > descriptor, but provided as a static configuration at the interrupt > controller level itself. OK. > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible. >
On 02/03/2021 at 11:28, Claudiu Beznea wrote: > Add DT bindings for Microchip External Interrupt Controller. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > .../interrupt-controller/mchp,eic.yaml | 74 +++++++++++++++++++ Nitpicking: use full vendor name in binding file name: microchip,eic.yaml > 1 file changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml [..] Regards,
On Tue, Mar 02, 2021 at 12:28:45PM +0200, Claudiu Beznea wrote: > Add DT bindings for Microchip External Interrupt Controller. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > .../interrupt-controller/mchp,eic.yaml | 74 +++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml > new file mode 100644 > index 000000000000..5a927817aa7d > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/mchp,eic.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip External Interrupt Controller > + > +maintainers: > + - Claudiu Beznea <claudiu.beznea@microchip.com> > + > +description: > + This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides > + support for handling up to 2 external interrupt lines. > + > +properties: > + compatible: > + enum: > + - microchip,sama7g5-eic > + > + reg: > + maxItems: 1 > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 3 > + description: > + The first cell is the input IRQ number (between 0 and 1), the second cell > + is the trigger type as defined in interrupt.txt present in this directory > + and the third cell is the glitch filter (1, 2, 4, 8) in clock cycles > + > + 'interrupts': Don't need quotes here. > + description: | > + Contains the GIC SPI IRQs mapped to the external interrupt lines. They > + should be specified sequentially from output 0 to output 1. > + minItems: 2 > + maxItems: 2 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: pclk > + > +required: > + - compatible > + - reg > + - interrupt-controller > + - '#interrupt-cells' > + - 'interrupts' Or here. > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/at91.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + eic: eic@e1628000 { interrupt-controller@... > + compatible = "microchip,sama7g5-eic"; > + reg = <0xe1628000 0x100>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; > + clock-names = "pclk"; > + }; > + > +... > -- > 2.25.1 >
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml new file mode 100644 index 000000000000..5a927817aa7d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mchp,eic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip External Interrupt Controller + +maintainers: + - Claudiu Beznea <claudiu.beznea@microchip.com> + +description: + This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides + support for handling up to 2 external interrupt lines. + +properties: + compatible: + enum: + - microchip,sama7g5-eic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + description: + The first cell is the input IRQ number (between 0 and 1), the second cell + is the trigger type as defined in interrupt.txt present in this directory + and the third cell is the glitch filter (1, 2, 4, 8) in clock cycles + + 'interrupts': + description: | + Contains the GIC SPI IRQs mapped to the external interrupt lines. They + should be specified sequentially from output 0 to output 1. + minItems: 2 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + const: pclk + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - 'interrupts' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/at91.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + eic: eic@e1628000 { + compatible = "microchip,sama7g5-eic"; + reg = <0xe1628000 0x100>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "pclk"; + }; + +...
Add DT bindings for Microchip External Interrupt Controller. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- .../interrupt-controller/mchp,eic.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml