From patchwork Wed Mar 3 17:09:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Thierry X-Patchwork-Id: 12114589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EE21C433DB for ; Wed, 3 Mar 2021 23:55:37 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0DA3D64F3F for ; Wed, 3 Mar 2021 23:55:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0DA3D64F3F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BOyZW7QG7CTELMrFzKF23CltaKDlVecjrBbRjTC8hzI=; b=JeM/MGrCc46EDGggMy0CIPuwW 5hQalYpVXzVeHc7GqQoWtJUteDbFRlCLjTbiNT6D1QIHQQdD3GD5/7cHU3AU/I95nKL/rgV8C/8dz hDpzt4Rll5wcL4ccvlrZtTTt4a4IRhlamIpW2VJvvzhnpk36OEeXEQm0qCMoqwBN3vMEaYU1KdYJh u4uHHOr5LFN4PxgpjomeskqpFjPEP8a9hXZZnxDwisNPUV+uR3H5/SdXgTeKM4xaezvOy/NIifC9j eLys6YVGbPof8AEFrirmoVtI7Cz5GW9SFqjbl9DR4oMLa8x+6cAkmUiH/q2jkLZh7sYYLztSRieUM iU/1AX60A==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lHbFQ-0071j0-Ek; Wed, 03 Mar 2021 23:49:44 +0000 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lHV0P-005jrY-8q for linux-arm-kernel@lists.infradead.org; Wed, 03 Mar 2021 17:09:54 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1614791388; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dRmeHncs6ezc68w5bwY/D71XAF3BdqJ0pJWy8Obs2Tk=; b=BW7Ia1P+uXwCrdfR2fB76xd4W8BgR1SnWiAGwASm8d8tJX4PBu0Gkc2oCh4y6gSEsmUY3c +N/rfi6T213jxPVgFFDKED+EwPejF6fnpqR3ppe27SoK/4/YgtM7wHE4TgYSbI6U2oVyFP sfNcw3hfaxZVK8vdWM4FpVXpws4XLjk= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-444-RZ7adL8yO5y6rRpgvzjZLA-1; Wed, 03 Mar 2021 12:09:46 -0500 X-MC-Unique: RZ7adL8yO5y6rRpgvzjZLA-1 Received: by mail-wr1-f72.google.com with SMTP id h5so4606955wrr.17 for ; Wed, 03 Mar 2021 09:09:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dRmeHncs6ezc68w5bwY/D71XAF3BdqJ0pJWy8Obs2Tk=; b=TsNCjIUWarsZLE0+J8fwSI3xwmEQfJSD2fl0Xx+GzVR2ZK+QwbS7ryPrjOZ+UPAX5Y g/adMgYAwOB/T6yuGOKvZ2B9/8OWz52Oz6uJ+vnF/WNp2pYwQw+MDF5pjHQQCfjtK6S9 D2ImuQlcFn7acsAjd8kGUY0DtZNNnsvaLZ3nGetRlKk3Pvp74G1v+E+62sWZ+T2+gj9K XHTQ04UN/c2H3uWoTOWlD7YXw6dnMdSjaodQt74YdCXBGl3tMDUkAWJcEmF/HvdczPUE BIhBlaFEG5Tv8rtE6oryGE3spX4NScrfgChjM5bB/BTdbwS0DkjZgHbJRChMjrmYDXMX HXPQ== X-Gm-Message-State: AOAM531EUx8QtE6dmYRVI5eRhgjYcJtcxfZUPF5h+X0qbpfn4XwhPsW8 Lo/V3rOANp7p528st5hDsCYiwvdDvUzt6E444DDzJNap2lBD1EYPI2YhCkSC+KDAv8Y8u35pbqB vx8vuKpjLjeHpCWs4Tf1PUu6lii3gHcbB1oE= X-Received: by 2002:adf:8b5c:: with SMTP id v28mr27521886wra.272.1614791385153; Wed, 03 Mar 2021 09:09:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJyLBLB5Lk8aQF0Nglz5/ZrWHAG0QUBwpg2ce/LTsqYabu/2WEp5jEOMEVwBmr4Dtzgc6p+Ixg== X-Received: by 2002:adf:8b5c:: with SMTP id v28mr27521875wra.272.1614791384974; Wed, 03 Mar 2021 09:09:44 -0800 (PST) Received: from redfedo.redhat.com ([2a01:cb14:499:3d00:cd47:f651:9d80:157a]) by smtp.gmail.com with ESMTPSA id r7sm33066226wre.25.2021.03.03.09.09.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 09:09:44 -0800 (PST) From: Julien Thierry To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, ardb@kernel.org, masahiroy@kernel.org, jpoimboe@redhat.com, peterz@infradead.org, ycote@redhat.com, Julien Thierry Subject: [RFC PATCH v2 05/13] objtool: arm64: Decode add/sub instructions Date: Wed, 3 Mar 2021 18:09:24 +0100 Message-Id: <20210303170932.1838634-6-jthierry@redhat.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210303170932.1838634-1-jthierry@redhat.com> References: <20210303170932.1838634-1-jthierry@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=jthierry@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Decode aarch64 additions and substractions and create stack_ops for instructions interacting with SP or FP. Signed-off-by: Julien Thierry --- tools/objtool/arch/arm64/decode.c | 94 +++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/tools/objtool/arch/arm64/decode.c b/tools/objtool/arch/arm64/decode.c index 3ec0254f7306..54eeb8704a42 100644 --- a/tools/objtool/arch/arm64/decode.c +++ b/tools/objtool/arch/arm64/decode.c @@ -23,6 +23,13 @@ #include "../../../arch/arm64/lib/insn.c" +static unsigned long sign_extend(unsigned long x, int nbits) +{ + unsigned long sign_bit = (x >> (nbits - 1)) & 1; + + return ((~0UL + (sign_bit ^ 1)) << nbits) | x; +} + bool arch_callee_saved_reg(unsigned char reg) { switch (reg) { @@ -98,6 +105,61 @@ int arch_decode_hint_reg(struct instruction *insn, u8 sp_reg) return -1; } +static struct stack_op *arm_make_add_op(enum aarch64_insn_register dest, + enum aarch64_insn_register src, + int val) +{ + struct stack_op *op; + + op = calloc(1, sizeof(*op)); + if (!op) { + WARN("calloc failed"); + return NULL; + } + op->dest.type = OP_DEST_REG; + op->dest.reg = dest; + op->src.reg = src; + op->src.type = val != 0 ? OP_SRC_ADD : OP_SRC_REG; + op->src.offset = val; + + return op; +} + +static int arm_decode_add_sub_imm(u32 instr, bool set_flags, + enum insn_type *type, + unsigned long *immediate, + struct list_head *ops_list) +{ + u32 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, instr); + u32 rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, instr); + + *type = INSN_OTHER; + *immediate = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_12, instr); + + if (instr & AARCH64_INSN_LSL_12) + *immediate <<= 12; + + if ((!set_flags && rd == AARCH64_INSN_REG_SP) || + rd == AARCH64_INSN_REG_FP || + rn == AARCH64_INSN_REG_FP || + rn == AARCH64_INSN_REG_SP) { + struct stack_op *op; + int value; + + if (aarch64_insn_is_subs_imm(instr) || aarch64_insn_is_sub_imm(instr)) + value = -*immediate; + else + value = *immediate; + + op = arm_make_add_op(rd, rn, value); + if (!op) + return -1; + list_add_tail(&op->list, ops_list); + } + + return 0; +} + int arch_decode_instruction(const struct elf *elf, const struct section *sec, unsigned long offset, unsigned int maxlen, unsigned int *len, enum insn_type *type, @@ -121,6 +183,38 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec, case AARCH64_INSN_CLS_UNKNOWN: WARN("can't decode instruction at %s:0x%lx", sec->name, offset); return -1; + case AARCH64_INSN_CLS_DP_IMM: + /* Mov register to and from SP are aliases of add_imm */ + if (aarch64_insn_is_add_imm(insn) || + aarch64_insn_is_sub_imm(insn)) + return arm_decode_add_sub_imm(insn, false, type, immediate, + ops_list); + else if (aarch64_insn_is_adds_imm(insn) || + aarch64_insn_is_subs_imm(insn)) + return arm_decode_add_sub_imm(insn, true, type, immediate, + ops_list); + else + *type = INSN_OTHER; + break; + case AARCH64_INSN_CLS_DP_REG: + if (aarch64_insn_is_mov_reg(insn)) { + enum aarch64_insn_register rd; + enum aarch64_insn_register rm; + + rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, insn); + rm = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RM, insn); + if (rd == AARCH64_INSN_REG_FP || rm == AARCH64_INSN_REG_FP) { + struct stack_op *op; + + op = arm_make_add_op(rd, rm, 0); + if (!op) + return -1; + list_add_tail(&op->list, ops_list); + break; + } + } + *type = INSN_OTHER; + break; default: *type = INSN_OTHER; break;