| Message ID | 20210307031353.12643-4-boger@wirenboard.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | sun8i: r40: second ethernet support | expand |
Hi, On Sun, Mar 07, 2021 at 06:13:53AM +0300, Evgeny Boger wrote: > R40 (aka V40, A40i, T3) has two different Ethernet IP > called EMAC and GMAC. > EMAC only support 10/100 Mbit in MII mode, > while GMAC support both 10/100 (MII) and 10/100/1000 (RGMII). > > In contrast to A10/A20 where GMAC and EMAC share the same pins > making EMAC somewhat pointless, on R40 EMAC can be routed to port H. > Both EMAC (on port H) and GMAC (on port A) > can be then enabled at the same time, allowing for two ethernet ports. > > Signed-off-by: Evgeny Boger <boger@wirenboard.com> > --- > arch/arm/boot/dts/sun8i-r40.dtsi | 53 ++++++++++++++++++++++++++++++++ > 1 file changed, 53 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi > index d5ad3b9efd12..c102c1510012 100644 > --- a/arch/arm/boot/dts/sun8i-r40.dtsi > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi > @@ -217,6 +217,20 @@ > #size-cells = <1>; > ranges; > > + sram_a: sram@0 { > + compatible = "mmio-sram"; > + reg = <0x00000000 0xc000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x00000000 0xc000>; > + > + emac_sram: sram-section@8000 { > + compatible = "allwinner,sun4i-a10-sram-a3-a4"; > + reg = <0x8000 0x4000>; > + status = "okay"; > + }; > + }; > + > sram_c: sram@1d00000 { > compatible = "mmio-sram"; > reg = <0x01d00000 0xd0000>; > @@ -541,6 +555,24 @@ > drive-strength = <40>; > }; > > + emac_ph_pins: emac-ph-pins { > + pins = "PH8", "PH9", "PH10", "PH11", > + "PH14", "PH15", "PH16", "PH17", > + "PH18","PH19", "PH20", "PH21", > + "PH22", "PH23", "PH24", "PH25", > + "PH26", "PH27"; > + function = "emac"; > + }; > + > + emac_pa_pins: emac-pa-pins { > + pins = "PA0", "PA1", "PA2", > + "PA3", "PA4", "PA5", "PA6", > + "PA7", "PA8", "PA9", "PA10", > + "PA11", "PA12", "PA13", "PA14", > + "PA15", "PA16"; > + function = "emac"; > + }; > + These nodes should be order alphabetically > i2c0_pins: i2c0-pins { > pins = "PB0", "PB1"; > function = "i2c0"; > @@ -885,6 +917,27 @@ > }; > }; > > + emac: ethernet@1c0b000 { > + syscon = <&ccu>; Why is the syscon needed? You weren't using it in the driver > + compatible = "allwinner,sun4i-a10-emac"; > + reg = <0x01c0b000 0x1000>; > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_EMAC>; > + resets = <&ccu RST_BUS_EMAC>; > + allwinner,sram = <&emac_sram 1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&emac_ph_pins>; If there's several options, we really can't enforce a default here, it should be in the board DTS. Maxime
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5ad3b9efd12..c102c1510012 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -217,6 +217,20 @@ #size-cells = <1>; ranges; + sram_a: sram@0 { + compatible = "mmio-sram"; + reg = <0x00000000 0xc000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00000000 0xc000>; + + emac_sram: sram-section@8000 { + compatible = "allwinner,sun4i-a10-sram-a3-a4"; + reg = <0x8000 0x4000>; + status = "okay"; + }; + }; + sram_c: sram@1d00000 { compatible = "mmio-sram"; reg = <0x01d00000 0xd0000>; @@ -541,6 +555,24 @@ drive-strength = <40>; }; + emac_ph_pins: emac-ph-pins { + pins = "PH8", "PH9", "PH10", "PH11", + "PH14", "PH15", "PH16", "PH17", + "PH18","PH19", "PH20", "PH21", + "PH22", "PH23", "PH24", "PH25", + "PH26", "PH27"; + function = "emac"; + }; + + emac_pa_pins: emac-pa-pins { + pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + function = "emac"; + }; + i2c0_pins: i2c0-pins { pins = "PB0", "PB1"; function = "i2c0"; @@ -885,6 +917,27 @@ }; }; + emac: ethernet@1c0b000 { + syscon = <&ccu>; + compatible = "allwinner,sun4i-a10-emac"; + reg = <0x01c0b000 0x1000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EMAC>; + resets = <&ccu RST_BUS_EMAC>; + allwinner,sram = <&emac_sram 1>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_ph_pins>; + status = "disabled"; + }; + + emac_mdio: mdio@1c0b080 { + compatible = "allwinner,sun4i-a10-mdio"; + reg = <0x01c0b080 0x14>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + mbus: dram-controller@1c62000 { compatible = "allwinner,sun8i-r40-mbus"; reg = <0x01c62000 0x1000>;
R40 (aka V40, A40i, T3) has two different Ethernet IP called EMAC and GMAC. EMAC only support 10/100 Mbit in MII mode, while GMAC support both 10/100 (MII) and 10/100/1000 (RGMII). In contrast to A10/A20 where GMAC and EMAC share the same pins making EMAC somewhat pointless, on R40 EMAC can be routed to port H. Both EMAC (on port H) and GMAC (on port A) can be then enabled at the same time, allowing for two ethernet ports. Signed-off-by: Evgeny Boger <boger@wirenboard.com> --- arch/arm/boot/dts/sun8i-r40.dtsi | 53 ++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+)