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[v5,16/36] arm64: asm: Provide set_sctlr_el2 macro

Message ID 20210315143536.214621-17-qperret@google.com (mailing list archive)
State New, archived
Headers show
Series KVM: arm64: A stage 2 for the host | expand

Commit Message

Quentin Perret March 15, 2021, 2:35 p.m. UTC
We will soon need to turn the EL2 stage 1 MMU on and off in nVHE
protected mode, so refactor the set_sctlr_el1 macro to make it usable
for that purpose.

Acked-by: Will Deacon <will@kernel.org>
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Quentin Perret <qperret@google.com>
 arch/arm64/include/asm/assembler.h | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)
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diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index ca31594d3d6c..fb651c1f26e9 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -676,11 +676,11 @@  USER(\label, ic	ivau, \tmp2)			// invalidate I line PoU
- * Set SCTLR_EL1 to the passed value, and invalidate the local icache
+ * Set SCTLR_ELx to the @reg value, and invalidate the local icache
  * in the process. This is called when setting the MMU on.
-.macro set_sctlr_el1, reg
-	msr	sctlr_el1, \reg
+.macro set_sctlr, sreg, reg
+	msr	\sreg, \reg
 	 * Invalidate the local I-cache so that any instructions fetched
@@ -692,6 +692,14 @@  USER(\label, ic	ivau, \tmp2)			// invalidate I line PoU
+.macro set_sctlr_el1, reg
+	set_sctlr sctlr_el1, \reg
+.macro set_sctlr_el2, reg
+	set_sctlr sctlr_el2, \reg
  * Check whether to yield to another runnable task from kernel mode NEON code
  * (which runs with preemption disabled).