diff mbox series

[v2,for-stable-v5.11] arm64: Unconditionally set virtual cpu id registers

Message ID 20210316134319.89472-1-vladimir.murzin@arm.com (mailing list archive)
State New, archived
Headers show
Series [v2,for-stable-v5.11] arm64: Unconditionally set virtual cpu id registers | expand

Commit Message

Vladimir Murzin March 16, 2021, 1:43 p.m. UTC
Commit 78869f0f0552 ("arm64: Extract parts of el2_setup into a macro")
reorganized el2 setup in such way that virtual cpu id registers set
only in nVHE, yet they used (and need) to be set irrespective VHE
support.

Fixes: 78869f0f0552 ("arm64: Extract parts of el2_setup into a macro")
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
Changelog

  v1 -> v2
     - Drop the reference to 32bit guests from commit message (per Marc)

There is no upstream fix since issue went away due to code there has
been reworked in 5.12: nVHE comes first, so virtual cpu id register
are always set.

Maintainers, please, Ack.

 arch/arm64/include/asm/el2_setup.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Marc Zyngier March 16, 2021, 1:52 p.m. UTC | #1
On Tue, 16 Mar 2021 13:43:19 +0000,
Vladimir Murzin <vladimir.murzin@arm.com> wrote:
> 
> Commit 78869f0f0552 ("arm64: Extract parts of el2_setup into a macro")
> reorganized el2 setup in such way that virtual cpu id registers set
> only in nVHE, yet they used (and need) to be set irrespective VHE
> support.
> 
> Fixes: 78869f0f0552 ("arm64: Extract parts of el2_setup into a macro")
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>

Reviewed-by: Marc Zyngier <maz@kernel.org>

Thanks,

	M.
Will Deacon March 17, 2021, 1:26 p.m. UTC | #2
On Tue, Mar 16, 2021 at 01:43:19PM +0000, Vladimir Murzin wrote:
> Commit 78869f0f0552 ("arm64: Extract parts of el2_setup into a macro")
> reorganized el2 setup in such way that virtual cpu id registers set
> only in nVHE, yet they used (and need) to be set irrespective VHE
> support.
> 
> Fixes: 78869f0f0552 ("arm64: Extract parts of el2_setup into a macro")
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
> Changelog
> 
>   v1 -> v2
>      - Drop the reference to 32bit guests from commit message (per Marc)
> 
> There is no upstream fix since issue went away due to code there has
> been reworked in 5.12: nVHE comes first, so virtual cpu id register
> are always set.
> 
> Maintainers, please, Ack.
> 
>  arch/arm64/include/asm/el2_setup.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Acked-by: Will Deacon <will@kernel.org>

It's a bit weird to have a patch in stable that isn't upstream, but I don't
see a better option here.

Will
Sasha Levin March 18, 2021, 12:57 p.m. UTC | #3
On Wed, Mar 17, 2021 at 01:26:15PM +0000, Will Deacon wrote:
>On Tue, Mar 16, 2021 at 01:43:19PM +0000, Vladimir Murzin wrote:
>> Commit 78869f0f0552 ("arm64: Extract parts of el2_setup into a macro")
>> reorganized el2 setup in such way that virtual cpu id registers set
>> only in nVHE, yet they used (and need) to be set irrespective VHE
>> support.
>>
>> Fixes: 78869f0f0552 ("arm64: Extract parts of el2_setup into a macro")
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>> ---
>> Changelog
>>
>>   v1 -> v2
>>      - Drop the reference to 32bit guests from commit message (per Marc)
>>
>> There is no upstream fix since issue went away due to code there has
>> been reworked in 5.12: nVHE comes first, so virtual cpu id register
>> are always set.
>>
>> Maintainers, please, Ack.
>>
>>  arch/arm64/include/asm/el2_setup.h | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>
>Acked-by: Will Deacon <will@kernel.org>
>
>It's a bit weird to have a patch in stable that isn't upstream, but I don't
>see a better option here.

Yes, I'd agree here - the commits that would need to be backported look
way too invasive.

I've queued it up, thanks.
Greg KH March 19, 2021, 9:45 a.m. UTC | #4
On Thu, Mar 18, 2021 at 08:57:00AM -0400, Sasha Levin wrote:
> On Wed, Mar 17, 2021 at 01:26:15PM +0000, Will Deacon wrote:
> > On Tue, Mar 16, 2021 at 01:43:19PM +0000, Vladimir Murzin wrote:
> > > Commit 78869f0f0552 ("arm64: Extract parts of el2_setup into a macro")
> > > reorganized el2 setup in such way that virtual cpu id registers set
> > > only in nVHE, yet they used (and need) to be set irrespective VHE
> > > support.
> > > 
> > > Fixes: 78869f0f0552 ("arm64: Extract parts of el2_setup into a macro")
> > > Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> > > ---
> > > Changelog
> > > 
> > >   v1 -> v2
> > >      - Drop the reference to 32bit guests from commit message (per Marc)
> > > 
> > > There is no upstream fix since issue went away due to code there has
> > > been reworked in 5.12: nVHE comes first, so virtual cpu id register
> > > are always set.
> > > 
> > > Maintainers, please, Ack.
> > > 
> > >  arch/arm64/include/asm/el2_setup.h | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > Acked-by: Will Deacon <will@kernel.org>
> > 
> > It's a bit weird to have a patch in stable that isn't upstream, but I don't
> > see a better option here.
> 
> Yes, I'd agree here - the commits that would need to be backported look
> way too invasive.
> 
> I've queued it up, thanks.

I don't see it, so I've added it as well...

thanks,

greg k-h
Greg Kroah-Hartman March 19, 2021, 9:58 a.m. UTC | #5
On Fri, Mar 19, 2021 at 10:52:29AM +0100, gregkh@linuxfoundation.org wrote:
> 
> This is a note to let you know that I've just added the patch titled
> 
>     arm64: Unconditionally set virtual cpu id registers
> 
> to the 4.14-stable tree which can be found at:
>     http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

OOps, no, wrong branch, my fault.

greg k-h
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index f988e94cdf9e..db87daca6b8c 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -113,7 +113,7 @@ 
 .endm
 
 /* Virtual CPU ID registers */
-.macro __init_el2_nvhe_idregs
+.macro __init_el2_idregs
 	mrs	x0, midr_el1
 	mrs	x1, mpidr_el1
 	msr	vpidr_el2, x0
@@ -165,6 +165,7 @@ 
 	__init_el2_stage2
 	__init_el2_gicv3
 	__init_el2_hstr
+	__init_el2_idregs
 
 	/*
 	 * When VHE is not in use, early init of EL2 needs to be done here.
@@ -173,7 +174,6 @@ 
 	 * will be done via the _EL1 system register aliases in __cpu_setup.
 	 */
 .ifeqs "\mode", "nvhe"
-	__init_el2_nvhe_idregs
 	__init_el2_nvhe_cptr
 	__init_el2_nvhe_sve
 	__init_el2_nvhe_prepare_eret