@@ -622,8 +622,8 @@ static int aic_init_cpu(unsigned int cpu)
/* Timer FIQs */
sysreg_clear_set(cntp_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK);
sysreg_clear_set(cntv_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK);
- sysreg_clear_set_s(SYS_CNTP_CTL_EL02, 0, ARCH_TIMER_CTRL_IT_MASK);
- sysreg_clear_set_s(SYS_CNTV_CTL_EL02, 0, ARCH_TIMER_CTRL_IT_MASK);
+ sysreg_clear_set_s(SYS_APL_VM_TMR_FIQ_ENA_EL1,
+ VM_TMR_FIQ_ENABLE_V | VM_TMR_FIQ_ENABLE_P, 0);
/* PMC FIQ */
sysreg_clear_set_s(SYS_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT,
@@ -633,6 +633,9 @@ static int aic_init_cpu(unsigned int cpu)
sysreg_clear_set_s(SYS_APL_UPMCR0_EL1, UPMCR0_IMODE,
FIELD_PREP(UPMCR0_IMODE, UPMCR0_IMODE_OFF));
+ /* Commit all of the above */
+ isb();
+
/*
* Make sure the kernel's idea of logical CPU order is the same as AIC's
* If we ever end up with a mismatch here, we will have to introduce
Instead of masking the guest timer at the source, take advantage of the SYS_APL_VM_TMR_FIQ_ENA_EL1 register and properly mask the timers at init time. For a good measure, add the missing ISB that synchronises all the previous sysreg accesses. Signed-off-by: Marc Zyngier <maz@kernel.org> --- drivers/irqchip/irq-apple-aic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)