From patchwork Thu Mar 18 05:04:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Benn X-Patchwork-Id: 12147355 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCEE9C433E0 for ; Thu, 18 Mar 2021 05:07:01 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23AC964EF2 for ; Thu, 18 Mar 2021 05:07:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 23AC964EF2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=qOVzxecvbx9EdeuEMlpIE7rLC/6T7a+nO3PCGlhqaeg=; b=asgT3fHZzu8lE+BNOQJhrMerOQ Kcvi48elL4eBcjUhCTEodA1yGJD5hPoia6zNoaysfbFNxRfRaNRAaoJ+XulbwdKt6FJRNcaVyZG9t X7Z3s8BbX+Y5npBOhkDBqC776Lq5LuKszKas8kZvwq7+kh70FdTOG8eyHlF+/l00VAziz/PeVHrum wvpjaWNptFW6dW7UFzj2g9fVgRLkarVFIS+nDEvNtYki26CqocWC8XO0e4eK+weRqgGXvyh2fZwiR 6CLq0Dg8YA7XZ9Y2KDS7dj2Ou5UmimCWU0SdB16UO/acphMbAOj/jS2kU0BGVk/+NjOa2WGDhIeMc 1DU1IdNg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lMkqX-004UOX-9x; Thu, 18 Mar 2021 05:05:21 +0000 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lMkqI-004UL9-0f for linux-arm-kernel@lists.infradead.org; Thu, 18 Mar 2021 05:05:08 +0000 Received: by mail-pj1-x102f.google.com with SMTP id ot17-20020a17090b3b51b0290109c9ac3c34so2104286pjb.4 for ; Wed, 17 Mar 2021 22:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=36PiNaX56sAO1ZzRuyV417jvibAlqz9NtYaUxMjW/tQ=; b=G3GSiT96OlxO0WheybnERDU3qhLUtZlctQzJo1uypnI8UMOlJ3edI19eS3bEVpsXvX R5Dqkr2T/5liBPM0ux+xjhTXMjHsJTvTPLd1KUJ1dF2u04aGEdeEVWtXAk/SA8IPrmJJ eBg1sHHHjTYHbphskw6f/cyfij7OwMBq9orsI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=36PiNaX56sAO1ZzRuyV417jvibAlqz9NtYaUxMjW/tQ=; b=bbqH9wcEIC5VYxGsTD3paUE2ZhjzJBVGvuq5Bvm9u6ggWcI6Lh1YzwQVQK58BBsZQf nKtNiXCKccSuAU90HpHhQxbYpIq4+q4pA7JPW2m0TrO/ujoCD7KKnWRnlCeFDAyXIYaB 4Zlc7YPsp+UKK3iyxTf89z2/rh2UuPuPQlW4MkBkn2lEuvBTnCF5uR37rYbPGFIUeEgQ YfDaFV6cMdU7u6zmTsy8lGGvK1mqma3BTq2o67Iw2n5PZTWJ7ljgrp3LVgz8yyKFfumN BZxttFOqFiyH+ekQpCAU3Pbd9RImHsJL7lsis8RwcHOKLriP0O46JQy/uzhOp9ts85Qr Td0A== X-Gm-Message-State: AOAM530irdBUBA9X3FRN0A8CJz22YJIF0jrF0rFgrLyaMpruPddov6nJ Zas1Nl8yJ9X9ov2G6RwIjMRtd2uLK5uyhg== X-Google-Smtp-Source: ABdhPJwpr/ryrnI0tlLSwK4DP8D2ZaAeUcsKYtfOQJjLULFE2FNTgiGdxmIWWCubfaDoBQc2dXVjAg== X-Received: by 2002:a17:90b:ece:: with SMTP id gz14mr2403234pjb.192.1616043903924; Wed, 17 Mar 2021 22:05:03 -0700 (PDT) Received: from evanbenn1.syd.corp.google.com ([2401:fa00:9:15:d0d6:1466:f005:1b0a]) by smtp.gmail.com with ESMTPSA id e8sm701450pgb.35.2021.03.17.22.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 22:05:03 -0700 (PDT) From: Evan Benn To: LKML Cc: Thomas Gleixner , Evan Benn , Yingjoe Chen , Julia Lawall , linux-arm-kernel@lists.infradead.org, Stanley Chu , Daniel Lezcano , Matthias Brugger , Viresh Kumar , Fabien Parent , linux-mediatek@lists.infradead.org, Alexey Klimov , Catalin Marinas , Russell King , Will Deacon Subject: [PATCH 1/2] drivers/clocksource/mediatek: Split mediatek drivers into 2 files Date: Thu, 18 Mar 2021 16:04:50 +1100 Message-Id: <20210318160414.1.Ia2a09ce93b47eac45308205820db0938d47604df@changeid> X-Mailer: git-send-email 2.31.0.rc2.261.g7f71774620-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210318_050506_722368_61DAF768 X-CRM114-Status: GOOD ( 22.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org mtk_gpt and mtk_syst drivers for mt6577 and mt6765 devices were not sharing any code. So split them into separate files. Signed-off-by: Evan Benn --- arch/arm/mach-mediatek/Kconfig | 3 +- arch/arm64/Kconfig.platforms | 3 +- drivers/clocksource/Kconfig | 13 +- drivers/clocksource/Makefile | 3 +- ...mer-mediatek.c => timer-mediatek-mt6577.c} | 100 ------------- drivers/clocksource/timer-mediatek-mt6765.c | 135 ++++++++++++++++++ 6 files changed, 151 insertions(+), 106 deletions(-) rename drivers/clocksource/{timer-mediatek.c => timer-mediatek-mt6577.c} (69%) create mode 100644 drivers/clocksource/timer-mediatek-mt6765.c diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 9e0f592d87d8..8686f992c4b6 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -4,7 +4,8 @@ menuconfig ARCH_MEDIATEK depends on ARCH_MULTI_V7 select ARM_GIC select PINCTRL - select MTK_TIMER + select TIMER_MEDIATEK_MT6577 + select TIMER_MEDIATEK_MT6765 select MFD_SYSCON help Support for Mediatek MT65xx & MT81xx SoCs diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index cdfd5fed457f..d4752375ab0b 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -161,7 +161,8 @@ config ARCH_MEDIATEK bool "MediaTek SoC Family" select ARM_GIC select PINCTRL - select MTK_TIMER + select TIMER_MEDIATEK_MT6577 + select TIMER_MEDIATEK_MT6765 help This enables support for MediaTek MT27xx, MT65xx, MT76xx & MT81xx ARMv8 SoCs diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 39aa21d01e05..d697c799284e 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -438,13 +438,20 @@ config OXNAS_RPS_TIMER config SYS_SUPPORTS_SH_CMT bool -config MTK_TIMER - bool "Mediatek timer driver" if COMPILE_TEST +config TIMER_MEDIATEK_MT6577 + bool "Mediatek mt6577 timer driver" if COMPILE_TEST depends on HAS_IOMEM select TIMER_OF select CLKSRC_MMIO help - Support for Mediatek timer driver. + Enables clocksource and clockevent driver for Mediatek mt6577 timer. + +config TIMER_MEDIATEK_MT6765 + bool "Mediatek mt6765 timer driver" if COMPILE_TEST + depends on HAS_IOMEM + select TIMER_OF + help + Enables clockevent driver for Mediatek mt6765 timer. config SPRD_TIMER bool "Spreadtrum timer driver" if EXPERT diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index c17ee32a7151..b1f06ce114f9 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -49,7 +49,8 @@ obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o obj-$(CONFIG_FSL_FTM_TIMER) += timer-fsl-ftm.o obj-$(CONFIG_VF_PIT_TIMER) += timer-vf-pit.o obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o -obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o +obj-$(CONFIG_TIMER_MEDIATEK_MT6577) += timer-mediatek-mt6577.o +obj-$(CONFIG_TIMER_MEDIATEK_MT6765) += timer-mediatek-mt6765.o obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek-mt6577.c similarity index 69% rename from drivers/clocksource/timer-mediatek.c rename to drivers/clocksource/timer-mediatek-mt6577.c index 9318edcd8963..9e5241d1876d 100644 --- a/drivers/clocksource/timer-mediatek.c +++ b/drivers/clocksource/timer-mediatek-mt6577.c @@ -47,86 +47,8 @@ #define GPT_CNT_REG(val) (0x08 + (0x10 * (val))) #define GPT_CMP_REG(val) (0x0C + (0x10 * (val))) -/* system timer */ -#define SYST_BASE (0x40) - -#define SYST_CON (SYST_BASE + 0x0) -#define SYST_VAL (SYST_BASE + 0x4) - -#define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON) -#define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL) - -/* - * SYST_CON_EN: Clock enable. Shall be set to - * - Start timer countdown. - * - Allow timeout ticks being updated. - * - Allow changing interrupt functions. - * - * SYST_CON_IRQ_EN: Set to allow interrupt. - * - * SYST_CON_IRQ_CLR: Set to clear interrupt. - */ -#define SYST_CON_EN BIT(0) -#define SYST_CON_IRQ_EN BIT(1) -#define SYST_CON_IRQ_CLR BIT(4) - static void __iomem *gpt_sched_reg __read_mostly; -static void mtk_syst_ack_irq(struct timer_of *to) -{ - /* Clear and disable interrupt */ - writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to)); -} - -static irqreturn_t mtk_syst_handler(int irq, void *dev_id) -{ - struct clock_event_device *clkevt = dev_id; - struct timer_of *to = to_timer_of(clkevt); - - mtk_syst_ack_irq(to); - clkevt->event_handler(clkevt); - - return IRQ_HANDLED; -} - -static int mtk_syst_clkevt_next_event(unsigned long ticks, - struct clock_event_device *clkevt) -{ - struct timer_of *to = to_timer_of(clkevt); - - /* Enable clock to allow timeout tick update later */ - writel(SYST_CON_EN, SYST_CON_REG(to)); - - /* - * Write new timeout ticks. Timer shall start countdown - * after timeout ticks are updated. - */ - writel(ticks, SYST_VAL_REG(to)); - - /* Enable interrupt */ - writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to)); - - return 0; -} - -static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt) -{ - /* Disable timer */ - writel(0, SYST_CON_REG(to_timer_of(clkevt))); - - return 0; -} - -static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt) -{ - return mtk_syst_clkevt_shutdown(clkevt); -} - -static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt) -{ - return 0; -} - static u64 notrace mtk_gpt_read_sched_clock(void) { return readl_relaxed(gpt_sched_reg); @@ -255,27 +177,6 @@ static struct timer_of to = { }, }; -static int __init mtk_syst_init(struct device_node *node) -{ - int ret; - - to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT; - to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown; - to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot; - to.clkevt.tick_resume = mtk_syst_clkevt_resume; - to.clkevt.set_next_event = mtk_syst_clkevt_next_event; - to.of_irq.handler = mtk_syst_handler; - - ret = timer_of_init(node, &to); - if (ret) - return ret; - - clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), - TIMER_SYNC_TICKS, 0xffffffff); - - return 0; -} - static int __init mtk_gpt_init(struct device_node *node) { int ret; @@ -310,4 +211,3 @@ static int __init mtk_gpt_init(struct device_node *node) return 0; } TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init); -TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init); diff --git a/drivers/clocksource/timer-mediatek-mt6765.c b/drivers/clocksource/timer-mediatek-mt6765.c new file mode 100644 index 000000000000..b4f22f226feb --- /dev/null +++ b/drivers/clocksource/timer-mediatek-mt6765.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Mediatek SoCs General-Purpose Timer handling. + * + * Copyright (C) 2014 Matthias Brugger + * + * Matthias Brugger + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include "timer-of.h" + +#define TIMER_SYNC_TICKS (3) + +/* system timer */ +#define SYST_BASE (0x40) + +#define SYST_CON (SYST_BASE + 0x0) +#define SYST_VAL (SYST_BASE + 0x4) + +#define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON) +#define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL) + +/* + * SYST_CON_EN: Clock enable. Shall be set to + * - Start timer countdown. + * - Allow timeout ticks being updated. + * - Allow changing interrupt functions. + * + * SYST_CON_IRQ_EN: Set to allow interrupt. + * + * SYST_CON_IRQ_CLR: Set to clear interrupt. + */ +#define SYST_CON_EN BIT(0) +#define SYST_CON_IRQ_EN BIT(1) +#define SYST_CON_IRQ_CLR BIT(4) + +static void mtk_syst_ack_irq(struct timer_of *to) +{ + /* Clear and disable interrupt */ + writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to)); +} + +static irqreturn_t mtk_syst_handler(int irq, void *dev_id) +{ + struct clock_event_device *clkevt = dev_id; + struct timer_of *to = to_timer_of(clkevt); + + mtk_syst_ack_irq(to); + clkevt->event_handler(clkevt); + + return IRQ_HANDLED; +} + +static int mtk_syst_clkevt_next_event(unsigned long ticks, + struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + /* Enable clock to allow timeout tick update later */ + writel(SYST_CON_EN, SYST_CON_REG(to)); + + /* + * Write new timeout ticks. Timer shall start countdown + * after timeout ticks are updated. + */ + writel(ticks, SYST_VAL_REG(to)); + + /* Enable interrupt */ + writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to)); + + return 0; +} + +static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt) +{ + /* Disable timer */ + writel(0, SYST_CON_REG(to_timer_of(clkevt))); + + return 0; +} + +static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt) +{ + return mtk_syst_clkevt_shutdown(clkevt); +} + +static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt) +{ + return 0; +} + +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + + .clkevt = { + .name = "mtk-clkevt", + .rating = 300, + .cpumask = cpu_possible_mask, + }, + + .of_irq = { + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, +}; + +static int __init mtk_syst_init(struct device_node *node) +{ + int ret; + + to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT; + to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown; + to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot; + to.clkevt.tick_resume = mtk_syst_clkevt_resume; + to.clkevt.set_next_event = mtk_syst_clkevt_next_event; + to.of_irq.handler = mtk_syst_handler; + + ret = timer_of_init(node, &to); + if (ret) + return ret; + + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), + TIMER_SYNC_TICKS, 0xffffffff); + + return 0; +} + +TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);