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Tue, 23 Mar 2021 05:57:02 -0800 Received: from MTKMBS06N1.mediatek.inc (172.21.101.129) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 06:57:01 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 21:56:59 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Mar 2021 21:56:59 +0800 From: Roger Lu To: Matthias Brugger , Enric Balletbo Serra , Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd , Philipp Zabel CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Nishanth Menon , Roger Lu , , , , , , Subject: [PATCH v13 6/7] arm64: dts: mt8192: add svs device information Date: Tue, 23 Mar 2021 21:56:56 +0800 Message-ID: <20210323135657.2701-7-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210323135657.2701-1-roger.lu@mediatek.com> References: <20210323135657.2701-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_135714_358323_C31DA36A X-CRM114-Status: GOOD ( 10.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org add compitable/reg/irq/clock/efuse/reset setting in svs node Signed-off-by: Roger Lu --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 2f0b4824a024..f3a339de8992 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -268,6 +268,14 @@ compatible = "mediatek,mt8192-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "mediatek,infra-reset", "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = < + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: svs */ + >; + }; }; pericfg: syscon@10003000 { @@ -362,6 +370,20 @@ status = "disabled"; }; + svs: svs@1100b000 { + compatible = "mediatek,mt8192-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, + <&lvts_e_data1>; + nvmem-cell-names = "svs-calibration-data", + "t-calibration-data"; + resets = <&infracfg_rst 0>; + reset-names = "svs_rst"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8192-spi", "mediatek,mt6765-spi"; @@ -473,6 +495,18 @@ status = "disable"; }; + efuse: efuse@11c10000 { + compatible = "mediatek,efuse"; + reg = <0 0x11c10000 0 0x1000>; + + lvts_e_data1: data1 { + reg = <0x1C0 0x58>; + }; + svs_calibration: calib@580 { + reg = <0x580 0x68>; + }; + }; + i2c3: i2c3@11cb0000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11cb0000 0 0x1000>,