diff mbox series

[v5,06/11] arm64: dts: rockchip: Fix power-controller node names for rk3399

Message ID 20210326091726.12531-1-zhangqing@rock-chips.com (mailing list archive)
State New, archived
Headers show
Series soc: rockchip: power-domain: add rk3568 powerdomains | expand

Commit Message

Elaine Zhang March 26, 2021, 9:17 a.m. UTC 
Use more generic names (as recommended in the device tree specification
or the binding documentation)

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 ++++++++++++------------
 1 file changed, 20 insertions(+), 20 deletions(-)

Comments

Enric Balletbo Serra March 26, 2021, 9:42 a.m. UTC | #1 
Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de
març 2021 a les 10:18:
>
> Use more generic names (as recommended in the device tree specification
> or the binding documentation)
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>

> ---
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 ++++++++++++------------
>  1 file changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index edbbf35fe19e..142f5593d48b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -971,26 +971,26 @@
>                         #size-cells = <0>;
>
>                         /* These power domains are grouped by VD_CENTER */
> -                       pd_iep@RK3399_PD_IEP {
> +                       power-domain@RK3399_PD_IEP {
>                                 reg = <RK3399_PD_IEP>;
>                                 clocks = <&cru ACLK_IEP>,
>                                          <&cru HCLK_IEP>;
>                                 pm_qos = <&qos_iep>;
>                         };
> -                       pd_rga@RK3399_PD_RGA {
> +                       power-domain@RK3399_PD_RGA {
>                                 reg = <RK3399_PD_RGA>;
>                                 clocks = <&cru ACLK_RGA>,
>                                          <&cru HCLK_RGA>;
>                                 pm_qos = <&qos_rga_r>,
>                                          <&qos_rga_w>;
>                         };
> -                       pd_vcodec@RK3399_PD_VCODEC {
> +                       power-domain@RK3399_PD_VCODEC {
>                                 reg = <RK3399_PD_VCODEC>;
>                                 clocks = <&cru ACLK_VCODEC>,
>                                          <&cru HCLK_VCODEC>;
>                                 pm_qos = <&qos_video_m0>;
>                         };
> -                       pd_vdu@RK3399_PD_VDU {
> +                       power-domain@RK3399_PD_VDU {
>                                 reg = <RK3399_PD_VDU>;
>                                 clocks = <&cru ACLK_VDU>,
>                                          <&cru HCLK_VDU>;
> @@ -999,94 +999,94 @@
>                         };
>
>                         /* These power domains are grouped by VD_GPU */
> -                       pd_gpu@RK3399_PD_GPU {
> +                       power-domain@RK3399_PD_GPU {
>                                 reg = <RK3399_PD_GPU>;
>                                 clocks = <&cru ACLK_GPU>;
>                                 pm_qos = <&qos_gpu>;
>                         };
>
>                         /* These power domains are grouped by VD_LOGIC */
> -                       pd_edp@RK3399_PD_EDP {
> +                       power-domain@RK3399_PD_EDP {
>                                 reg = <RK3399_PD_EDP>;
>                                 clocks = <&cru PCLK_EDP_CTRL>;
>                         };
> -                       pd_emmc@RK3399_PD_EMMC {
> +                       power-domain@RK3399_PD_EMMC {
>                                 reg = <RK3399_PD_EMMC>;
>                                 clocks = <&cru ACLK_EMMC>;
>                                 pm_qos = <&qos_emmc>;
>                         };
> -                       pd_gmac@RK3399_PD_GMAC {
> +                       power-domain@RK3399_PD_GMAC {
>                                 reg = <RK3399_PD_GMAC>;
>                                 clocks = <&cru ACLK_GMAC>,
>                                          <&cru PCLK_GMAC>;
>                                 pm_qos = <&qos_gmac>;
>                         };
> -                       pd_sd@RK3399_PD_SD {
> +                       power-domain@RK3399_PD_SD {
>                                 reg = <RK3399_PD_SD>;
>                                 clocks = <&cru HCLK_SDMMC>,
>                                          <&cru SCLK_SDMMC>;
>                                 pm_qos = <&qos_sd>;
>                         };
> -                       pd_sdioaudio@RK3399_PD_SDIOAUDIO {
> +                       power-domain@RK3399_PD_SDIOAUDIO {
>                                 reg = <RK3399_PD_SDIOAUDIO>;
>                                 clocks = <&cru HCLK_SDIO>;
>                                 pm_qos = <&qos_sdioaudio>;
>                         };
> -                       pd_tcpc0@RK3399_PD_TCPD0 {
> +                       power-domain@RK3399_PD_TCPD0 {
>                                 reg = <RK3399_PD_TCPD0>;
>                                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
>                                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
>                         };
> -                       pd_tcpc1@RK3399_PD_TCPD1 {
> +                       power-domain@RK3399_PD_TCPD1 {
>                                 reg = <RK3399_PD_TCPD1>;
>                                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
>                                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
>                         };
> -                       pd_usb3@RK3399_PD_USB3 {
> +                       power-domain@RK3399_PD_USB3 {
>                                 reg = <RK3399_PD_USB3>;
>                                 clocks = <&cru ACLK_USB3>;
>                                 pm_qos = <&qos_usb_otg0>,
>                                          <&qos_usb_otg1>;
>                         };
> -                       pd_vio@RK3399_PD_VIO {
> +                       power-domain@RK3399_PD_VIO {
>                                 reg = <RK3399_PD_VIO>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
>
> -                               pd_hdcp@RK3399_PD_HDCP {
> +                               power-domain@RK3399_PD_HDCP {
>                                         reg = <RK3399_PD_HDCP>;
>                                         clocks = <&cru ACLK_HDCP>,
>                                                  <&cru HCLK_HDCP>,
>                                                  <&cru PCLK_HDCP>;
>                                         pm_qos = <&qos_hdcp>;
>                                 };
> -                               pd_isp0@RK3399_PD_ISP0 {
> +                               power-domain@RK3399_PD_ISP0 {
>                                         reg = <RK3399_PD_ISP0>;
>                                         clocks = <&cru ACLK_ISP0>,
>                                                  <&cru HCLK_ISP0>;
>                                         pm_qos = <&qos_isp0_m0>,
>                                                  <&qos_isp0_m1>;
>                                 };
> -                               pd_isp1@RK3399_PD_ISP1 {
> +                               power-domain@RK3399_PD_ISP1 {
>                                         reg = <RK3399_PD_ISP1>;
>                                         clocks = <&cru ACLK_ISP1>,
>                                                  <&cru HCLK_ISP1>;
>                                         pm_qos = <&qos_isp1_m0>,
>                                                  <&qos_isp1_m1>;
>                                 };
> -                               pd_vo@RK3399_PD_VO {
> +                               power-domain@RK3399_PD_VO {
>                                         reg = <RK3399_PD_VO>;
>                                         #address-cells = <1>;
>                                         #size-cells = <0>;
>
> -                                       pd_vopb@RK3399_PD_VOPB {
> +                                       power-domain@RK3399_PD_VOPB {
>                                                 reg = <RK3399_PD_VOPB>;
>                                                 clocks = <&cru ACLK_VOP0>,
>                                                          <&cru HCLK_VOP0>;
>                                                 pm_qos = <&qos_vop_big_r>,
>                                                          <&qos_vop_big_w>;
>                                         };
> -                                       pd_vopl@RK3399_PD_VOPL {
> +                                       power-domain@RK3399_PD_VOPL {
>                                                 reg = <RK3399_PD_VOPL>;
>                                                 clocks = <&cru ACLK_VOP1>,
>                                                          <&cru HCLK_VOP1>;
> --
> 2.17.1
>
>
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index edbbf35fe19e..142f5593d48b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -971,26 +971,26 @@ 
 			#size-cells = <0>;
 
 			/* These power domains are grouped by VD_CENTER */
-			pd_iep@RK3399_PD_IEP {
+			power-domain@RK3399_PD_IEP {
 				reg = <RK3399_PD_IEP>;
 				clocks = <&cru ACLK_IEP>,
 					 <&cru HCLK_IEP>;
 				pm_qos = <&qos_iep>;
 			};
-			pd_rga@RK3399_PD_RGA {
+			power-domain@RK3399_PD_RGA {
 				reg = <RK3399_PD_RGA>;
 				clocks = <&cru ACLK_RGA>,
 					 <&cru HCLK_RGA>;
 				pm_qos = <&qos_rga_r>,
 					 <&qos_rga_w>;
 			};
-			pd_vcodec@RK3399_PD_VCODEC {
+			power-domain@RK3399_PD_VCODEC {
 				reg = <RK3399_PD_VCODEC>;
 				clocks = <&cru ACLK_VCODEC>,
 					 <&cru HCLK_VCODEC>;
 				pm_qos = <&qos_video_m0>;
 			};
-			pd_vdu@RK3399_PD_VDU {
+			power-domain@RK3399_PD_VDU {
 				reg = <RK3399_PD_VDU>;
 				clocks = <&cru ACLK_VDU>,
 					 <&cru HCLK_VDU>;
@@ -999,94 +999,94 @@ 
 			};
 
 			/* These power domains are grouped by VD_GPU */
-			pd_gpu@RK3399_PD_GPU {
+			power-domain@RK3399_PD_GPU {
 				reg = <RK3399_PD_GPU>;
 				clocks = <&cru ACLK_GPU>;
 				pm_qos = <&qos_gpu>;
 			};
 
 			/* These power domains are grouped by VD_LOGIC */
-			pd_edp@RK3399_PD_EDP {
+			power-domain@RK3399_PD_EDP {
 				reg = <RK3399_PD_EDP>;
 				clocks = <&cru PCLK_EDP_CTRL>;
 			};
-			pd_emmc@RK3399_PD_EMMC {
+			power-domain@RK3399_PD_EMMC {
 				reg = <RK3399_PD_EMMC>;
 				clocks = <&cru ACLK_EMMC>;
 				pm_qos = <&qos_emmc>;
 			};
-			pd_gmac@RK3399_PD_GMAC {
+			power-domain@RK3399_PD_GMAC {
 				reg = <RK3399_PD_GMAC>;
 				clocks = <&cru ACLK_GMAC>,
 					 <&cru PCLK_GMAC>;
 				pm_qos = <&qos_gmac>;
 			};
-			pd_sd@RK3399_PD_SD {
+			power-domain@RK3399_PD_SD {
 				reg = <RK3399_PD_SD>;
 				clocks = <&cru HCLK_SDMMC>,
 					 <&cru SCLK_SDMMC>;
 				pm_qos = <&qos_sd>;
 			};
-			pd_sdioaudio@RK3399_PD_SDIOAUDIO {
+			power-domain@RK3399_PD_SDIOAUDIO {
 				reg = <RK3399_PD_SDIOAUDIO>;
 				clocks = <&cru HCLK_SDIO>;
 				pm_qos = <&qos_sdioaudio>;
 			};
-			pd_tcpc0@RK3399_PD_TCPD0 {
+			power-domain@RK3399_PD_TCPD0 {
 				reg = <RK3399_PD_TCPD0>;
 				clocks = <&cru SCLK_UPHY0_TCPDCORE>,
 					 <&cru SCLK_UPHY0_TCPDPHY_REF>;
 			};
-			pd_tcpc1@RK3399_PD_TCPD1 {
+			power-domain@RK3399_PD_TCPD1 {
 				reg = <RK3399_PD_TCPD1>;
 				clocks = <&cru SCLK_UPHY1_TCPDCORE>,
 					 <&cru SCLK_UPHY1_TCPDPHY_REF>;
 			};
-			pd_usb3@RK3399_PD_USB3 {
+			power-domain@RK3399_PD_USB3 {
 				reg = <RK3399_PD_USB3>;
 				clocks = <&cru ACLK_USB3>;
 				pm_qos = <&qos_usb_otg0>,
 					 <&qos_usb_otg1>;
 			};
-			pd_vio@RK3399_PD_VIO {
+			power-domain@RK3399_PD_VIO {
 				reg = <RK3399_PD_VIO>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				pd_hdcp@RK3399_PD_HDCP {
+				power-domain@RK3399_PD_HDCP {
 					reg = <RK3399_PD_HDCP>;
 					clocks = <&cru ACLK_HDCP>,
 						 <&cru HCLK_HDCP>,
 						 <&cru PCLK_HDCP>;
 					pm_qos = <&qos_hdcp>;
 				};
-				pd_isp0@RK3399_PD_ISP0 {
+				power-domain@RK3399_PD_ISP0 {
 					reg = <RK3399_PD_ISP0>;
 					clocks = <&cru ACLK_ISP0>,
 						 <&cru HCLK_ISP0>;
 					pm_qos = <&qos_isp0_m0>,
 						 <&qos_isp0_m1>;
 				};
-				pd_isp1@RK3399_PD_ISP1 {
+				power-domain@RK3399_PD_ISP1 {
 					reg = <RK3399_PD_ISP1>;
 					clocks = <&cru ACLK_ISP1>,
 						 <&cru HCLK_ISP1>;
 					pm_qos = <&qos_isp1_m0>,
 						 <&qos_isp1_m1>;
 				};
-				pd_vo@RK3399_PD_VO {
+				power-domain@RK3399_PD_VO {
 					reg = <RK3399_PD_VO>;
 					#address-cells = <1>;
 					#size-cells = <0>;
 
-					pd_vopb@RK3399_PD_VOPB {
+					power-domain@RK3399_PD_VOPB {
 						reg = <RK3399_PD_VOPB>;
 						clocks = <&cru ACLK_VOP0>,
 							 <&cru HCLK_VOP0>;
 						pm_qos = <&qos_vop_big_r>,
 							 <&qos_vop_big_w>;
 					};
-					pd_vopl@RK3399_PD_VOPL {
+					power-domain@RK3399_PD_VOPL {
 						reg = <RK3399_PD_VOPL>;
 						clocks = <&cru ACLK_VOP1>,
 							 <&cru HCLK_VOP1>;