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Sun, 28 Mar 2021 18:59:59 -0700 (PDT) From: Brad Larson To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, linus.walleij@linaro.org, bgolaszewski@baylibre.com, broonie@kernel.org, fancer.lancer@gmail.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net, brad@pensando.io, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/13] dt-bindings: spi: cadence-qspi: Add support for Pensando Elba SoC Date: Sun, 28 Mar 2021 18:59:35 -0700 Message-Id: <20210329015938.20316-11-brad@pensando.io> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210329015938.20316-1-brad@pensando.io> References: <20210329015938.20316-1-brad@pensando.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210329_114131_917082_762A8167 X-CRM114-Status: GOOD ( 25.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add new vendor Pensando Systems Elba SoC compatible string and convert to json-schema. Signed-off-by: Brad Larson --- .../bindings/spi/cadence-quadspi.txt | 68 -------- .../bindings/spi/cadence-quadspi.yaml | 153 ++++++++++++++++++ 2 files changed, 153 insertions(+), 68 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt deleted file mode 100644 index 8ace832a2d80..000000000000 --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Cadence Quad SPI controller - -Required properties: -- compatible : should be one of the following: - Generic default - "cdns,qspi-nor". - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". - For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". - For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". -- reg : Contains two entries, each of which is a tuple consisting of a - physical address and length. The first entry is the address and - length of the controller register set. The second entry is the - address and length of the QSPI Controller data area. -- interrupts : Unit interrupt specifier for the controller interrupt. -- clocks : phandle to the Quad SPI clock. -- cdns,fifo-depth : Size of the data FIFO in words. -- cdns,fifo-width : Bus width of the data FIFO in bytes. -- cdns,trigger-address : 32-bit indirect AHB trigger address. - -Optional properties: -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch - the read data rather than the QSPI clock. Make sure that QSPI return - clock is populated on the board before using this property. - -Optional subnodes: -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional -custom properties: -- cdns,read-delay : Delay for read capture logic, in clock cycles -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master - mode chip select outputs are de-asserted between - transactions. -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being - de-activated and the activation of another. -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current - transaction and deasserting the device chip select - (qspi_n_ss_out). -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low - and first bit transfer. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include either "qspi" and/or "qspi-ocp". - -Example: - - qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; - interrupts = <0 151 4>; - clocks = <&qspi_clk>; - cdns,is-decoded-cs; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; - reset-names = "qspi", "qspi-ocp"; - - flash0: n25q00@0 { - ... - cdns,read-delay = <4>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml new file mode 100644 index 000000000000..94d631045153 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence Quad SPI controller + +maintainers: + - Ramuthevar Vadivel Murugan + - Brad Larson + +properties: + compatible: + contains: + enum: + - cdns,qspi-nor # Generic default + - ti,k2g-qspi # TI 66AK2G SoC + - ti,am654-ospi # TI AM654 SoC + - intel,lgm-qspi # Intel LGM SoC + - pensando,cdns-qspi # Pensando Elba SoC + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + minItems: 2 + maxItems: 2 + description: | + Contains two entries, each of which is a tuple consisting of a + physical address and length. The first entry is the address and + length of the controller register set. The second entry is the + address and length of the QSPI Controller data area. + + interrupts: + maxItems: 1 + description: Unit interrupt specifier for the controller interrupt + + clocks: + description: phandle to the Quad SPI clock + + cdns,fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Size of the data FIFO in words + + cdns,fifo-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Bus width of the data FIFO in bytes + + cdns,trigger-address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: 32-bit indirect AHB trigger address + + cdns,is-decoded-cs: + $ref: /schemas/types.yaml#/definitions/flag + description: Flag to indicate whether decoder is used or not + + cdns,rclk-en: + description: + Flag to indicate that QSPI return clock is used to latch the + read data rather than the QSPI clock. Make sure that QSPI return + clock is populated on the board before using this property + $ref: /schemas/types.yaml#/definitions/flag + + # Subnodes of the Cadence Quad SPI controller are spi slave nodes + # with additional custom properties + cdns,read-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Delay for read capture logic, in clock cycles + + cdns,tshsl-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay in nanoseconds for the length that the master mode chip + select outputs are de-asserted between transactions + + cdns,tsd2d-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay in nanoseconds between one chip select being de-activated + and the activation of another. + + cdns,tchsh-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay in nanoseconds between last bit of current transaction and + deasserting the device chip select (qspi_n_ss_out). + + cdns,tslch-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay in nanoseconds between setting qspi_n_ss_out low and first + bit transfer. + + resets: + items: + - description: qspi reset + - description: qspi-ocp reset + + reset-names: + items: + - const: qspi + - const: qspi-ocp + +required: + - compatible + - reg + - interrupts + - clocks + - cdns,fifo-depth + - cdns,fifo-width + - cdns,trigger-address + +patternProperties: + "^.*@[0-9]+$": + type: object + +additionalProperties: false + +examples: + - | + #include + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,is-decoded-cs; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>; + reset-names = "qspi", "qspi-ocp"; + + flash0: mt25q@0 { + compatible = "jdec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; + };