clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback

Commit Message

Quanyang Wang March 31, 2021, 9 a.m. UTC

From: Quanyang Wang <[e-mail]>

The round_rate callback should only perform rate calculation and not
involve calling zynqmp_pll_set_mode to change the pll mode. So let's
move zynqmp_pll_set_mode out of round_rate and to set_rate callback.

Reported-by: Laurent Pinchart <[e-mail]>
Signed-off-by: Quanyang Wang <[e-mail]>
---
 drivers/clk/zynqmp/pll.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Stephen Boyd April 1, 2021, 1:48 a.m. UTC | #1

Quoting [e-mail] (2021-03-31 02:00:18)
> From: Quanyang Wang <[e-mail]>
> 
> The round_rate callback should only perform rate calculation and not
> involve calling zynqmp_pll_set_mode to change the pll mode. So let's
> move zynqmp_pll_set_mode out of round_rate and to set_rate callback.
> 
> Reported-by: Laurent Pinchart <[e-mail]>
> Signed-off-by: Quanyang Wang <[e-mail]>
> ---

Any Fixes tag?

Quanyang Wang April 1, 2021, 2:01 a.m. UTC | #2

Hi Stephen,

On 4/1/21 9:48 AM, Stephen Boyd wrote:
> Quoting [e-mail] (2021-03-31 02:00:18)
>> From: Quanyang Wang <[e-mail]>
>>
>> The round_rate callback should only perform rate calculation and not
>> involve calling zynqmp_pll_set_mode to change the pll mode. So let's
>> move zynqmp_pll_set_mode out of round_rate and to set_rate callback.
>>
>> Reported-by: Laurent Pinchart <[e-mail]>
>> Signed-off-by: Quanyang Wang <[e-mail]>
>> ---
> Any Fixes tag?

Thanks for your reminder. I will add Fixes tag at the V2 version patch.

Thanks,

Quanyang

Patch

diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index fb16ddbb7e2d..1aea5c137b69 100644
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -104,9 +104,7 @@  static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 	/* Enable the fractional mode if needed */
 	rate_div = (rate * FRAC_DIV) / *prate;
 	f = rate_div % FRAC_DIV;
-	zynqmp_pll_set_mode(hw, !!f);
-
-	if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
+	if (f) {
 		if (rate > PS_PLL_VCO_MAX) {
 			fbdiv = rate / PS_PLL_VCO_MAX;
 			rate = rate / (fbdiv + 1);
@@ -177,10 +175,12 @@  static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	long rate_div, frac, m, f;
 	int ret;
 
-	if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
-		rate_div = (rate * FRAC_DIV) / parent_rate;
+	rate_div = (rate * FRAC_DIV) / parent_rate;
+	f = rate_div % FRAC_DIV;
+	zynqmp_pll_set_mode(hw, !!f);
+
+	if (f) {
 		m = rate_div / FRAC_DIV;
-		f = rate_div % FRAC_DIV;
 		m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
 		rate = parent_rate * m;
 		frac = (parent_rate * f) / FRAC_DIV;