From patchwork Wed Mar 31 10:58:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12175241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FA96C433DB for ; Wed, 31 Mar 2021 11:03:56 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A43F461994 for ; Wed, 31 Mar 2021 11:03:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A43F461994 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wou71JWR/HnFEQrlGk8RSUip0TQgAXnFqb1964SIxKE=; b=O7lgKt6OOpbWFcSKuKzPzLVQo 4buRgFQu5oH+PvDFJsAUxT2qghwq6qWoWSKYYLReYmVqRJg4K4jzAzk/IE4TYFw3P8cvefg7e8f/0 hAOYios/7haMKxKJ4W393md+8aTbswwwzphbqsSAei9BXOM1q61vt27sn7qUsy8tId2hQlGnEkYlr NxTxqzEL+OYpo/dgKmc2foOlMOffcVg5Aqe8J83iw76xFWnz4lawAgCJeK6m+9xJ5rM9N9AukgKM/ gOohjwtnprwPKWBT8wvSGozLa0wcAzt5N9PqgxFuvuOhvm3RWQBg9SZYQbL/gfHC5AQT1Uw7X+RXO 5H1PkRJzw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRYbY-006JuZ-TW; Wed, 31 Mar 2021 11:01:45 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRYZX-006JMJ-HN for linux-arm-kernel@lists.infradead.org; Wed, 31 Mar 2021 10:59:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617188379; x=1648724379; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NVdLR/4vBiZXHdxKzbg48TM13jojIDCbZRf2vOwtXD0=; b=zL45dG1l43ketcxCXT09/lZLNd+2mjw9fGsRYjFXratNAOx2zcoysamj qokQ8R38WY47v2nqnK2G1MphGR0QoLrU5a4po+XEi93saIPNqfu5p5L1x pctMM1ybBNM65MMRk6k1VQWJknQRftkkuZ+SqXbeXLD3dExy+p1pXqpJ/ cEjK0YTES4rkGsQax+wStAG8wLU01LOi3W8X3DgUhlburIQ95InaO7aBW AvzfhKJiBg97j0MzvYTCCBRC3t0Cvi8z5mlTPoAedAPZb5o0oFTNTNu0j PFRlkouLyc1awDZO6YvmIPuNkVv47xfhTvV6JBOCs+pTY33+2FiWPCD5M A==; IronPort-SDR: WrHGpatz0+gXv79qwOEhq/Jdn3MWaGK1FGtD/W3BRtkR2XjIIKHKSDvViPi0mwGk2oOEfehoaG /3V3GKnPIl3qYP+mhNJaGY08gU0QhHo/N3aHB+isQ/YwhpB7Af15E7Uf92UDIxiJQkT8QuZYDQ g1NMEJ0F1ih77rhkp8AM4TCz/5b31I1tdP1MWWZRwbGjkKQR9PkwCxLxs1AntYB+f7D6xMtwq0 2HBekLtNkt/U1OXXKJlyCAJsdvbwiBrk4Qz1i4htcWZrkk2xi6rYqPpHvdjgvIrpQ51bo6h22p 7zc= X-IronPort-AV: E=Sophos;i="5.81,293,1610434800"; d="scan'208";a="121233940" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 31 Mar 2021 03:59:38 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Wed, 31 Mar 2021 03:59:38 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Wed, 31 Mar 2021 03:59:36 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH 10/24] ARM: at91: sfrbu: add sfrbu registers definitions for sama7g5 Date: Wed, 31 Mar 2021 13:58:54 +0300 Message-ID: <20210331105908.23027-11-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210331105908.23027-1-claudiu.beznea@microchip.com> References: <20210331105908.23027-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210331_115939_973583_F3FD4E7A X-CRM114-Status: GOOD ( 11.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add SFRBU registers definitions for SAMA7G5. Signed-off-by: Claudiu Beznea --- include/soc/at91/sama7-sfrbu.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 include/soc/at91/sama7-sfrbu.h diff --git a/include/soc/at91/sama7-sfrbu.h b/include/soc/at91/sama7-sfrbu.h new file mode 100644 index 000000000000..76b740810d34 --- /dev/null +++ b/include/soc/at91/sama7-sfrbu.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Microchip SAMA7 SFRBU registers offsets and bit definitions. + * + * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries + * + * Author: Claudu Beznea + */ + +#ifndef __SAMA7_SFRBU_H__ +#define __SAMA7_SFRBU_H__ + +#ifdef CONFIG_SOC_SAMA7 + +#define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */ +#define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */ +#define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */ +#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ +#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ + +#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ +#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ +#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ +#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ +#define AT91_SFRBU_PD_VALUE_MSK (0x3) +#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ + +#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ +#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ + +#endif /* CONFIG_SOC_SAMA7 */ + +#endif /* __SAMA7_SFRBU_H__ */ +