From patchwork Mon Apr 5 15:51:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12183211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 609FAC433ED for ; Mon, 5 Apr 2021 16:06:25 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 226C9613B8 for ; Mon, 5 Apr 2021 16:06:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 226C9613B8 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xoTwbd58iUN+JK5t8SU0HpVKzwXtpOxsm1RjB8hS2vI=; b=Iw9QTQG+rIaXck5BBxKHA0OzX 5lqDb7FN0nqkRUPYYHJmSB1Pi+qMx9NRYsojxkLAHTUHmJYgOYQGFEkm+VGT6txvuINDoOp4C5kCr byZ32iE+LdvwTFnu1B5FCO69PLONa+b0DxarLY0zvK/OG3havf7H2Fvv1/+/5bfyuMEElNjPdNvPO HFqK+hwFtesljMDrQPa2HPLljB66SHjYLLWrGx7jxVe/OjgbPHNDROW4uE6hMxF3qor8xDFLpYzMx jscgH8JFkVGRpiBnOZKo+aql5wb9PMfF3k7ySOAhnr6p3l8ZWFBo3Z0L21G7GdiEucxfSE/w0Onsj 89sjnk9Gg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lTRi5-00HaGu-4H; Mon, 05 Apr 2021 16:04:17 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lTRck-00HYcC-Is for linux-arm-kernel@lists.infradead.org; Mon, 05 Apr 2021 15:58:55 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617638326; x=1649174326; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JB3dr1U/DWt6qBqOVHSGXJCImGHTndPyXb9YXu64Mas=; b=S2rTXHDHTShKCw+sJP/OZLV/J/2a7dFWUlKZL9rq1/TdIrChZG6z6VJk nra+xpeIbcFzbArew3yYcGPi61Ix1YU+W8oJiVDMtrkYRulGIw43LeoNp XwpN2YN2FOfaalQAIGQi+5/+qPxx5MBq5M7DuLSu0JnQlpkyulUHXqtz5 ya25UZvGj/aZkkCAXRhRPl/OLqB9J/yenUUMe+8oh0EqdSXogSooZtLiz er32txb1OnMYyjupQu7Ie58/zdW6nHvKCXcTzirgsLCzspDggjrp4yWSD R59lasn6bK+4PurRH4Lwgd8wFGgFFrziIAfUHE2OxRGSCTeL/EoUhIOIB Q==; IronPort-SDR: 9/jxeI8/LRrrN+Dtft/TboiQNFFs4IBBcAqcCQKFaYQ7NWiwmZzkv2Hv5dIYCwDCjmo5B1G+7n M86IzkJB31e9zB7gTzKmH2An/SpVd3xnWUv0GBuEO85ty6Gc0ABK1TwoAvwNGrcaqBr0Tdhud/ HXMXVEHXqTaE2XEYPeXfeOnFrrUvmMzKH0lIsaXQ+we2FDM7wBu7Nph6sV3DzbnHL2pR7hJkPb fVYOhu93+nhZdE/mYDTa36tkOsSFFFMH1nFOiLBud4MiwDNLXQE7I6kMjW6v2pb89TdyVMbbF2 Mi0= X-IronPort-AV: E=Sophos;i="5.81,307,1610434800"; d="scan'208";a="112482201" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Apr 2021 08:58:45 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 5 Apr 2021 08:58:44 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Mon, 5 Apr 2021 08:58:13 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH v2 26/30] media: atmel: atmel-isc-regs: add additional fields for sama7g5 type pipeline Date: Mon, 5 Apr 2021 18:51:01 +0300 Message-ID: <20210405155105.162529-27-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210405155105.162529-1-eugen.hristev@microchip.com> References: <20210405155105.162529-1-eugen.hristev@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210405_165847_210393_5ABE8A85 X-CRM114-Status: UNSURE ( 7.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add additional fields for registers present in sama7g5 type pipeline. Extend register masks for additional bits in sama7g5 type pipeline registers. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index 457eed74cda9..5f99bf7717c1 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -289,8 +289,18 @@ #define ISC_RLP_CFG_MODE_ARGB32 0xa #define ISC_RLP_CFG_MODE_YYCC 0xb #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc +#define ISC_RLP_CFG_MODE_YCYC 0xd #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) +#define ISC_RLP_CFG_LSH BIT(5) + +#define ISC_RLP_CFG_YMODE_YUYV (3 << 6) +#define ISC_RLP_CFG_YMODE_YVYU (2 << 6) +#define ISC_RLP_CFG_YMODE_VYUY (0 << 6) +#define ISC_RLP_CFG_YMODE_UYVY (1 << 6) + +#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6) + /* Offset for HIS register specific to sama5d2 product */ #define ISC_SAMA5D2_HIS_OFFSET 0 /* Histogram Control Register */ @@ -332,13 +342,15 @@ #define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4) #define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4) #define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4) -#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4) +#define ISC_DCFG_YMBSIZE_BEATS32 (0x4 << 4) +#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4) #define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8) #define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8) #define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8) #define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8) -#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8) +#define ISC_DCFG_CMBSIZE_BEATS32 (0x4 << 8) +#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8) /* DMA Control Register */ #define ISC_DCTRL 0x000003e4