| Message ID | 20210405163357.30902-1-weifeng.voon@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [net-next] net: intel: Enable SERDES PHY rx clk for PSE | expand |
On Tue, Apr 06, 2021 at 12:33:57AM +0800, Voon Weifeng wrote: > > EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up > sequence and vice versa. > > Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> > --- > drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 ++++++++++ > drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | 1 + > 2 files changed, 11 insertions(+) > Why not use "stmmac: intel" for the commit message header? > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c > b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c > index add95e20548d..a4fec5fe0779 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c > @@ -153,6 +153,11 @@ static int intel_serdes_powerup(struct net_device > *ndev, void *priv_data) > return data; > } > > + /* PSE only - ungate SGMII PHY Rx Clock */ > + if (intel_priv->is_pse) > + mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, > + 0, SERDES_PHY_RX_CLK); > + > return 0; > } > > @@ -168,6 +173,11 @@ static void intel_serdes_powerdown(struct > net_device *ndev, void *intel_data) > > serdes_phy_addr = intel_priv->mdio_adhoc_addr; > > + /* PSE only - gate SGMII PHY Rx Clock */ > + if (intel_priv->is_pse) > + mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, > + SERDES_PHY_RX_CLK, 0); > + > /* move power state to P3 */ > data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h > b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h > index e723096c0b15..542acb8ce467 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h > @@ -14,6 +14,7 @@ > > /* SERDES defines */ > #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal > */ > +#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */ > #define SERDES_RST BIT(2) /* Serdes Reset */ > #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power > state*/ > #define SERDES_PWR_ST_SHIFT 4 > -- > 2.17.1
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index add95e20548d..a4fec5fe0779 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -153,6 +153,11 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) return data; } + /* PSE only - ungate SGMII PHY Rx Clock */ + if (intel_priv->is_pse) + mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, + 0, SERDES_PHY_RX_CLK); + return 0; } @@ -168,6 +173,11 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) serdes_phy_addr = intel_priv->mdio_adhoc_addr; + /* PSE only - gate SGMII PHY Rx Clock */ + if (intel_priv->is_pse) + mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, + SERDES_PHY_RX_CLK, 0); + /* move power state to P3 */ data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h index e723096c0b15..542acb8ce467 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h @@ -14,6 +14,7 @@ /* SERDES defines */ #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */ +#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */ #define SERDES_RST BIT(2) /* Serdes Reset */ #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/ #define SERDES_PWR_ST_SHIFT 4
EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up sequence and vice versa. Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> --- drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 ++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | 1 + 2 files changed, 11 insertions(+)