| Message ID | 20210409111345.294472-17-claudiu.beznea@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: at91: pm: add support for sama7g5 | expand |
On Fri, Apr 09, 2021 at 02:13:37PM +0300, Claudiu Beznea wrote: > Add RAM controller and RAM PHY controller DT bindings. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- > .../devicetree/bindings/arm/atmel-sysregs.txt | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt > index 807264a78edc..7cd55a760d41 100644 > --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt > +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt > @@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties: > "atmel,at91sam9260-sdramc", > "atmel,at91sam9g45-ddramc", > "atmel,sama5d3-ddramc", > - "microchip,sam9x60-ddramc" > + "microchip,sam9x60-ddramc", > + "microchip,sama7g5-uddrc" > - reg: Should contain registers location and length > > Examples: > @@ -55,6 +56,18 @@ Examples: > reg = <0xffffe800 0x200>; > }; > > +RAMC PHY Controller required properties: > +- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon" > +- reg: Should contain registers location and length > + > +Example: > + > + ddr3phy: ddr3phy@e3804000 { > + compatible = "microchip,sama7g5-ddr3phy", "syscon"; > + reg = <0xe3804000 0x1000>; > + status = "okay"; Really need an example for this? If so, drop 'status'. > +}; > + > SHDWC Shutdown Controller > > required properties: > -- > 2.25.1 >
On 12.04.2021 19:02, Rob Herring wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Fri, Apr 09, 2021 at 02:13:37PM +0300, Claudiu Beznea wrote: >> Add RAM controller and RAM PHY controller DT bindings. >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> >> --- >> .../devicetree/bindings/arm/atmel-sysregs.txt | 15 ++++++++++++++- >> 1 file changed, 14 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt >> index 807264a78edc..7cd55a760d41 100644 >> --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt >> +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt >> @@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties: >> "atmel,at91sam9260-sdramc", >> "atmel,at91sam9g45-ddramc", >> "atmel,sama5d3-ddramc", >> - "microchip,sam9x60-ddramc" >> + "microchip,sam9x60-ddramc", >> + "microchip,sama7g5-uddrc" >> - reg: Should contain registers location and length >> >> Examples: >> @@ -55,6 +56,18 @@ Examples: >> reg = <0xffffe800 0x200>; >> }; >> >> +RAMC PHY Controller required properties: >> +- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon" >> +- reg: Should contain registers location and length >> + >> +Example: >> + >> + ddr3phy: ddr3phy@e3804000 { >> + compatible = "microchip,sama7g5-ddr3phy", "syscon"; >> + reg = <0xe3804000 0x1000>; >> + status = "okay"; > > Really need an example for this? If so, drop 'status'. The self-refresh code needs the address for this, this is why I've added it. The status is not needed so, as you suggested, I will remove it. Thank you, Claudiu > >> +}; >> + >> SHDWC Shutdown Controller >> >> required properties: >> -- >> 2.25.1 >>
diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 807264a78edc..7cd55a760d41 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties: "atmel,at91sam9260-sdramc", "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", - "microchip,sam9x60-ddramc" + "microchip,sam9x60-ddramc", + "microchip,sama7g5-uddrc" - reg: Should contain registers location and length Examples: @@ -55,6 +56,18 @@ Examples: reg = <0xffffe800 0x200>; }; +RAMC PHY Controller required properties: +- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon" +- reg: Should contain registers location and length + +Example: + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7g5-ddr3phy", "syscon"; + reg = <0xe3804000 0x1000>; + status = "okay"; +}; + SHDWC Shutdown Controller required properties:
Add RAM controller and RAM PHY controller DT bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- .../devicetree/bindings/arm/atmel-sysregs.txt | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)