diff mbox series

[boot-wrapper,3/5] gic-v3: Prepare for gicv3 with EL2

Message ID 20210420072438.183086-4-jaxson.han@arm.com (mailing list archive)
State New
Headers show
Series Add Armv8-R AArch64 support | expand

Commit Message

Jaxson Han April 20, 2021, 7:24 a.m. UTC
This is a preparation for allowing boot-wrapper configuring the gicv3
with EL2.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
---
 arch/aarch32/include/asm/gic-v3.h |  7 ++++++
 arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++---
 gic-v3.c                          |  2 +-
 3 files changed, 43 insertions(+), 4 deletions(-)

Comments

Andre Przywara April 26, 2021, 11:48 a.m. UTC | #1
On Tue, 20 Apr 2021 15:24:36 +0800
Jaxson Han <jaxson.han@arm.com> wrote:

> This is a preparation for allowing boot-wrapper configuring the gicv3
> with EL2.

The GIC is always confusing, so can you please give some more
background here? The introduction of ICC_SRE_EL2 looks straight-forward
enough, but the change to the ICC_CTLR_RESET register deserves some
comments, I guess.

Cheers,
Andre

> Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> ---
>  arch/aarch32/include/asm/gic-v3.h |  7 ++++++
>  arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++---
>  gic-v3.c                          |  2 +-
>  3 files changed, 43 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
> index ec9a327..86abe09 100644
> --- a/arch/aarch32/include/asm/gic-v3.h
> +++ b/arch/aarch32/include/asm/gic-v3.h
> @@ -9,6 +9,8 @@
>  #ifndef __ASM_AARCH32_GICV3_H
>  #define __ASM_AARCH32_GICV3_H
>  
> +#define ICC_CTLR_RESET	(0UL)
> +
>  static inline uint32_t gic_read_icc_sre(void)
>  {
>  	uint32_t val;
> @@ -26,4 +28,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
>  	asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));
>  }
>  
> +static inline void gic_init_icc_ctlr()
> +{
> +	gic_write_icc_ctlr(ICC_CTLR_RESET);
> +}
> +
>  #endif
> diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
> index e743c02..b3dfbd3 100644
> --- a/arch/aarch64/include/asm/gic-v3.h
> +++ b/arch/aarch64/include/asm/gic-v3.h
> @@ -15,21 +15,53 @@
>  #define ICC_CTLR_EL3	"S3_6_C12_C12_4"
>  #define ICC_PMR_EL1	"S3_0_C4_C6_0"
>  
> +#define ICC_CTLR_EL3_RESET	(0UL)
> +#define ICC_CTLR_EL1_RESET	(0UL)
> +
> +static inline uint32_t current_el(void)
> +{
> +	uint32_t val;
> +
> +	asm volatile ("mrs %0, CurrentEL" : "=r" (val));
> +	return val;
> +}
> +
>  static inline uint32_t gic_read_icc_sre(void)
>  {
>  	uint32_t val;
> -	asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
> +
> +	if(current_el() == CURRENTEL_EL3)
> +		asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
> +	else
> +		asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val));
> +
>  	return val;
>  }
>  
>  static inline void gic_write_icc_sre(uint32_t val)
>  {
> -	asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
> +	if(current_el() == CURRENTEL_EL3)
> +		asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
> +	else
> +		asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
>  }
>  
> -static inline void gic_write_icc_ctlr(uint32_t val)
> +static inline void gic_write_icc_ctlr_el3(uint32_t val)
>  {
>  	asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));
>  }
>  
> +static inline void gic_write_icc_ctlr_el1(uint32_t val)
> +{
> +	asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val));
> +}
> +
> +static inline void gic_init_icc_ctlr()
> +{
> +	if(current_el() == CURRENTEL_EL3)
> +		gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET);
> +	else
> +		gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET);
> +}
> +
>  #endif
> diff --git a/gic-v3.c b/gic-v3.c
> index ae2d2bc..4850572 100644
> --- a/gic-v3.c
> +++ b/gic-v3.c
> @@ -121,6 +121,6 @@ void gic_secure_init(void)
>  	gic_write_icc_sre(sre);
>  	isb();
>  
> -	gic_write_icc_ctlr(0);
> +	gic_init_icc_ctlr();
>  	isb();
>  }
Jaxson Han April 28, 2021, 3:30 a.m. UTC | #2
Hi Andre,

> -----Original Message-----
> From: Andre Przywara <andre.przywara@arm.com>
> Sent: Monday, April 26, 2021 7:48 PM
> To: Jaxson Han <Jaxson.Han@arm.com>
> Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> Subject: Re: [boot-wrapper PATCH 3/5] gic-v3: Prepare for gicv3 with EL2
> 
> On Tue, 20 Apr 2021 15:24:36 +0800
> Jaxson Han <jaxson.han@arm.com> wrote:
> 
> > This is a preparation for allowing boot-wrapper configuring the gicv3
> > with EL2.
> 
> The GIC is always confusing, so can you please give some more background
> here? The introduction of ICC_SRE_EL2 looks straight-forward enough, but
> the change to the ICC_CTLR_RESET register deserves some comments, I guess.

Right, I will put more details here.

Thanks,
Jaxson

> 
> Cheers,
> Andre
> 
> > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > ---
> >  arch/aarch32/include/asm/gic-v3.h |  7 ++++++
> > arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++-
> --
> >  gic-v3.c                          |  2 +-
> >  3 files changed, 43 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/aarch32/include/asm/gic-v3.h
> > b/arch/aarch32/include/asm/gic-v3.h
> > index ec9a327..86abe09 100644
> > --- a/arch/aarch32/include/asm/gic-v3.h
> > +++ b/arch/aarch32/include/asm/gic-v3.h
> > @@ -9,6 +9,8 @@
> >  #ifndef __ASM_AARCH32_GICV3_H
> >  #define __ASM_AARCH32_GICV3_H
> >
> > +#define ICC_CTLR_RESET	(0UL)
> > +
> >  static inline uint32_t gic_read_icc_sre(void)  {
> >  	uint32_t val;
> > @@ -26,4 +28,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
> >  	asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));  }
> >
> > +static inline void gic_init_icc_ctlr() {
> > +	gic_write_icc_ctlr(ICC_CTLR_RESET);
> > +}
> > +
> >  #endif
> > diff --git a/arch/aarch64/include/asm/gic-v3.h
> > b/arch/aarch64/include/asm/gic-v3.h
> > index e743c02..b3dfbd3 100644
> > --- a/arch/aarch64/include/asm/gic-v3.h
> > +++ b/arch/aarch64/include/asm/gic-v3.h
> > @@ -15,21 +15,53 @@
> >  #define ICC_CTLR_EL3	"S3_6_C12_C12_4"
> >  #define ICC_PMR_EL1	"S3_0_C4_C6_0"
> >
> > +#define ICC_CTLR_EL3_RESET	(0UL)
> > +#define ICC_CTLR_EL1_RESET	(0UL)
> > +
> > +static inline uint32_t current_el(void) {
> > +	uint32_t val;
> > +
> > +	asm volatile ("mrs %0, CurrentEL" : "=r" (val));
> > +	return val;
> > +}
> > +
> >  static inline uint32_t gic_read_icc_sre(void)  {
> >  	uint32_t val;
> > -	asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
> > +
> > +	if(current_el() == CURRENTEL_EL3)
> > +		asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
> > +	else
> > +		asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val));
> > +
> >  	return val;
> >  }
> >
> >  static inline void gic_write_icc_sre(uint32_t val)  {
> > -	asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
> > +	if(current_el() == CURRENTEL_EL3)
> > +		asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
> > +	else
> > +		asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
> >  }
> >
> > -static inline void gic_write_icc_ctlr(uint32_t val)
> > +static inline void gic_write_icc_ctlr_el3(uint32_t val)
> >  {
> >  	asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));  }
> >
> > +static inline void gic_write_icc_ctlr_el1(uint32_t val) {
> > +	asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val)); }
> > +
> > +static inline void gic_init_icc_ctlr() {
> > +	if(current_el() == CURRENTEL_EL3)
> > +		gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET);
> > +	else
> > +		gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET);
> > +}
> > +
> >  #endif
> > diff --git a/gic-v3.c b/gic-v3.c
> > index ae2d2bc..4850572 100644
> > --- a/gic-v3.c
> > +++ b/gic-v3.c
> > @@ -121,6 +121,6 @@ void gic_secure_init(void)
> >  	gic_write_icc_sre(sre);
> >  	isb();
> >
> > -	gic_write_icc_ctlr(0);
> > +	gic_init_icc_ctlr();
> >  	isb();
> >  }
diff mbox series

Patch

diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
index ec9a327..86abe09 100644
--- a/arch/aarch32/include/asm/gic-v3.h
+++ b/arch/aarch32/include/asm/gic-v3.h
@@ -9,6 +9,8 @@ 
 #ifndef __ASM_AARCH32_GICV3_H
 #define __ASM_AARCH32_GICV3_H
 
+#define ICC_CTLR_RESET	(0UL)
+
 static inline uint32_t gic_read_icc_sre(void)
 {
 	uint32_t val;
@@ -26,4 +28,9 @@  static inline void gic_write_icc_ctlr(uint32_t val)
 	asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));
 }
 
+static inline void gic_init_icc_ctlr()
+{
+	gic_write_icc_ctlr(ICC_CTLR_RESET);
+}
+
 #endif
diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
index e743c02..b3dfbd3 100644
--- a/arch/aarch64/include/asm/gic-v3.h
+++ b/arch/aarch64/include/asm/gic-v3.h
@@ -15,21 +15,53 @@ 
 #define ICC_CTLR_EL3	"S3_6_C12_C12_4"
 #define ICC_PMR_EL1	"S3_0_C4_C6_0"
 
+#define ICC_CTLR_EL3_RESET	(0UL)
+#define ICC_CTLR_EL1_RESET	(0UL)
+
+static inline uint32_t current_el(void)
+{
+	uint32_t val;
+
+	asm volatile ("mrs %0, CurrentEL" : "=r" (val));
+	return val;
+}
+
 static inline uint32_t gic_read_icc_sre(void)
 {
 	uint32_t val;
-	asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
+
+	if(current_el() == CURRENTEL_EL3)
+		asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
+	else
+		asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val));
+
 	return val;
 }
 
 static inline void gic_write_icc_sre(uint32_t val)
 {
-	asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
+	if(current_el() == CURRENTEL_EL3)
+		asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
+	else
+		asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
 }
 
-static inline void gic_write_icc_ctlr(uint32_t val)
+static inline void gic_write_icc_ctlr_el3(uint32_t val)
 {
 	asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));
 }
 
+static inline void gic_write_icc_ctlr_el1(uint32_t val)
+{
+	asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val));
+}
+
+static inline void gic_init_icc_ctlr()
+{
+	if(current_el() == CURRENTEL_EL3)
+		gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET);
+	else
+		gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET);
+}
+
 #endif
diff --git a/gic-v3.c b/gic-v3.c
index ae2d2bc..4850572 100644
--- a/gic-v3.c
+++ b/gic-v3.c
@@ -121,6 +121,6 @@  void gic_secure_init(void)
 	gic_write_icc_sre(sre);
 	isb();
 
-	gic_write_icc_ctlr(0);
+	gic_init_icc_ctlr();
 	isb();
 }