From patchwork Tue Apr 20 07:24:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaxson Han X-Patchwork-Id: 12213495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DF24C433ED for ; Tue, 20 Apr 2021 07:27:51 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CD84D60238 for ; Tue, 20 Apr 2021 07:27:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CD84D60238 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TJc63Co8I64EqUodgLPKBxsQ5GZjtFslVF1QYb/goRs=; b=M6slIXHd2zlUiPZPqQkP2g4g6 fKF0C/IQHjLcheIAfClZDYN4lv0i2BtxnKCj9DB3081BOXsjr6/hP35ZD+ZcNqRiqRdCmUMLc2WC1 XRczgUUWhTCnHqphZiNgcMJ0G/o2le0JsVm9QWNChrHgK94IQHRLtBxZoCT+o8LptInCiffi/9/qJ WGkBapkgY6UPxvrvtFIUHh/uuc5eZ0RIEWXu3gRAEjKFIfS4Cue5DkxBWuU1fLTx7wHljMGn3ZHYK 13RFk93HhoZvFjIgf6ZR7xF4HlU0AMrk+dmt6nJw32h+ehZhauV1E1wzoWq/jq44JmLMKeyywPIr0 w7G5aA73Q==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lYklk-00BSWD-8R; Tue, 20 Apr 2021 07:26:00 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lYkkx-00BSPO-2M for linux-arm-kernel@desiato.infradead.org; Tue, 20 Apr 2021 07:25:12 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-Type:Content-ID:Content-Description; bh=b0vZTMorNF36PL4FhNJ4XFc4eogQwHRbcSdUA+28jAM=; b=rxcDOJazbXYohc6vfTftXDx78W vl6Kf80q4n2pWFfxfxb54eq8QvYrjP9jOD2Ep+jrqW4rEwUiSdhxRCBduKVzVAeTCUIuAqfZaXlAX JhC1O7xVSpG7HgIXq0Aeqdr1zdiOPTIpHARTehN0Ur3gdaQP7QKqIgC/9mMog3ML5LR4PeuMtkBOu LWIhb7/fHJdSj5F5rL9RgGpyihUYZ+ZDBqxBMg8epjkD6QSusgbR2w33BXNuBVlhy4uujaVT7TWKm soAPR0g5Kha0u9W8PhcfdNolWr0tITYSSrupdNbY4SrKmCdfoIRoRFVUBBMOnBZKgfvAGyw0381fP MiHQCaQA==; Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lYkko-00BsTa-0U for linux-arm-kernel@lists.infradead.org; Tue, 20 Apr 2021 07:25:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 823D816F3; Tue, 20 Apr 2021 00:24:59 -0700 (PDT) Received: from optiplex-7070.shanghai.arm.com (optiplex-7070.shanghai.arm.com [10.169.188.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AAAD33F85F; Tue, 20 Apr 2021 00:24:57 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, andre.przywara@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH 3/5] gic-v3: Prepare for gicv3 with EL2 Date: Tue, 20 Apr 2021 15:24:36 +0800 Message-Id: <20210420072438.183086-4-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210420072438.183086-1-jaxson.han@arm.com> References: <20210420072438.183086-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210420_002502_115728_D967137F X-CRM114-Status: UNSURE ( 9.02 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a preparation for allowing boot-wrapper configuring the gicv3 with EL2. Signed-off-by: Jaxson Han --- arch/aarch32/include/asm/gic-v3.h | 7 ++++++ arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++--- gic-v3.c | 2 +- 3 files changed, 43 insertions(+), 4 deletions(-) diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h index ec9a327..86abe09 100644 --- a/arch/aarch32/include/asm/gic-v3.h +++ b/arch/aarch32/include/asm/gic-v3.h @@ -9,6 +9,8 @@ #ifndef __ASM_AARCH32_GICV3_H #define __ASM_AARCH32_GICV3_H +#define ICC_CTLR_RESET (0UL) + static inline uint32_t gic_read_icc_sre(void) { uint32_t val; @@ -26,4 +28,9 @@ static inline void gic_write_icc_ctlr(uint32_t val) asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val)); } +static inline void gic_init_icc_ctlr() +{ + gic_write_icc_ctlr(ICC_CTLR_RESET); +} + #endif diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h index e743c02..b3dfbd3 100644 --- a/arch/aarch64/include/asm/gic-v3.h +++ b/arch/aarch64/include/asm/gic-v3.h @@ -15,21 +15,53 @@ #define ICC_CTLR_EL3 "S3_6_C12_C12_4" #define ICC_PMR_EL1 "S3_0_C4_C6_0" +#define ICC_CTLR_EL3_RESET (0UL) +#define ICC_CTLR_EL1_RESET (0UL) + +static inline uint32_t current_el(void) +{ + uint32_t val; + + asm volatile ("mrs %0, CurrentEL" : "=r" (val)); + return val; +} + static inline uint32_t gic_read_icc_sre(void) { uint32_t val; - asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val)); + + if(current_el() == CURRENTEL_EL3) + asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val)); + else + asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val)); + return val; } static inline void gic_write_icc_sre(uint32_t val) { - asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); + if(current_el() == CURRENTEL_EL3) + asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); + else + asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val)); } -static inline void gic_write_icc_ctlr(uint32_t val) +static inline void gic_write_icc_ctlr_el3(uint32_t val) { asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val)); } +static inline void gic_write_icc_ctlr_el1(uint32_t val) +{ + asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val)); +} + +static inline void gic_init_icc_ctlr() +{ + if(current_el() == CURRENTEL_EL3) + gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET); + else + gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET); +} + #endif diff --git a/gic-v3.c b/gic-v3.c index ae2d2bc..4850572 100644 --- a/gic-v3.c +++ b/gic-v3.c @@ -121,6 +121,6 @@ void gic_secure_init(void) gic_write_icc_sre(sre); isb(); - gic_write_icc_ctlr(0); + gic_init_icc_ctlr(); isb(); }