| Message ID | 20210505093855.8416-1-catalin.marinas@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [aarch64,boot-wrapper] aarch64: Enable access to allocation tags if MTE is present | expand |
On Wed, May 05, 2021 at 10:38:55AM +0100, Catalin Marinas wrote: > SCR_EL3.ATA must be set so that software can access the allocation > (in-memory) MTE tags. > > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Thanks; applied. Mark. > --- > arch/aarch64/boot.S | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > index fd7133d1725c..a9264de937be 100644 > --- a/arch/aarch64/boot.S > +++ b/arch/aarch64/boot.S > @@ -61,6 +61,14 @@ _start: > cbz x1, 1f > > orr x0, x0, #(1 << 27) // FGT enable > +1: > + /* Enable MTE if present */ > + mrs x10, id_aa64pfr1_el1 > + ubfx x10, x10, #8, #4 > + cmp x10, #2 > + b.lt 1f > + > + orr x0, x0, #(1 << 26) // ATA enable > 1: > #ifndef KERNEL_32 > orr x0, x0, #(1 << 10) // 64-bit EL2
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index fd7133d1725c..a9264de937be 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -61,6 +61,14 @@ _start: cbz x1, 1f orr x0, x0, #(1 << 27) // FGT enable +1: + /* Enable MTE if present */ + mrs x10, id_aa64pfr1_el1 + ubfx x10, x10, #8, #4 + cmp x10, #2 + b.lt 1f + + orr x0, x0, #(1 << 26) // ATA enable 1: #ifndef KERNEL_32 orr x0, x0, #(1 << 10) // 64-bit EL2
SCR_EL3.ATA must be set so that software can access the allocation (in-memory) MTE tags. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> --- arch/aarch64/boot.S | 8 ++++++++ 1 file changed, 8 insertions(+)