diff mbox series

[RFC,4/4] arm64: dts: imx8mn: Enable blt-ctl power domains

Message ID 20210509144711.2192991-5-aford173@gmail.com (mailing list archive)
State New, archived
Headers show
Series soc: imx8mn: Add additional power domains | expand

Commit Message

Adam Ford May 9, 2021, 2:47 p.m. UTC
There are a few blk-ctl power domains required for peripherals
like ISI, CSI, DSI, and LCDIF.  These new power domains require
dispmix, and mipi from the gpcv2 controller in order to operate.
Add them all.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
Note: This series is an RFC because the 8MN hangs when resuming
from suspend, and I am looking for suggestions and feedback
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 7f8e7e24dadf..d7d91fb9b7b6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -646,6 +646,29 @@  pgc_gpumix: power-domain@2 {
 							 <&clk IMX8MN_CLK_GPU_AHB>;
 						resets = <&src IMX8MQ_RESET_GPU_RESET>;
 					};
+					
+					pgc_dispmix: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
+						clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+							 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+							 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+						assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>,
+								  <&clk IMX8MN_CLK_DISP_AXI>,
+								  <&clk IMX8MN_CLK_DISP_APB>;
+						assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>,
+									  <&clk IMX8MN_SYS_PLL2_1000M>,
+									  <&clk IMX8MN_SYS_PLL1_800M>;
+						assigned-clock-rate = <594000000>,
+									<500000000>,
+									<200000000>;
+                                       };
+
+                                       pgc_mipi: power-domain@4 {
+                                               #power-domain-cells = <0>;
+                                               reg = <IMX8MN_POWER_DOMAIN_MIPI>;
+                                               power-domains = <&pgc_dispmix>;
+                                       };
 				};
 			};
 		};
@@ -990,6 +1013,18 @@  aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges;
 
+			dispmix_blk_ctl: blk-ctl@32e28000 {
+				compatible = "fsl,imx8mn-dispmix-blk-ctl", "syscon";
+				reg = <0x32e28000 0x100>;
+				#power-domain-cells = <1>;
+				power-domains = <&pgc_dispmix>, <&pgc_mipi>;
+				power-domain-names = "dispmix", "mipi";
+				clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+				clock-names = "disp", "axi", "apb";
+			};
+
 			usbotg1: usb@32e40000 {
 				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
 				reg = <0x32e40000 0x200>;