| Message ID | 20210514224759.9987-3-s-anna@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add ICSSG MDIO nodes on AM65x & J721E SoCs | expand |
On 15/05/2021 01:47, Suman Anna wrote: > The ICSSGs on K3 J721E SoCs contain an MDIO controller that can > be used to control external PHYs associated with the Industrial > Ethernet peripherals within each ICSSG instance. The MDIO module > used within the ICSSG is similar to the MDIO Controller used > in TI Davinci SoCs. A bus frequency of 1 MHz is chosen for the > MDIO operations. > > The nodes are added and enabled in the common k3-j721e-main.dtsi > file by default, and disabled in the existing J721E board dts > file. These nodes need pinctrl lines, and so should be enabled > only on boards where they are actually wired and pinned out for > ICSSG Ethernet. Any new board dts file should disable these if > they are not sure. > > Signed-off-by: Suman Anna <s-anna@ti.com> > --- > .../dts/ti/k3-j721e-common-proc-board.dts | 8 ++++++++ > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 +++++++++++++++++++ > 2 files changed, 28 insertions(+) > Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 60764366e22b..c9bcff36f442 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -718,3 +718,11 @@ &pcie3_ep { &dss { status = "disabled"; }; + +&icssg0_mdio { + status = "disabled"; +}; + +&icssg1_mdio { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index c2aa45a3ac79..e00ff3d963ab 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1792,6 +1792,16 @@ tx_pru0_1: txpru@c000 { reg-names = "iram", "control", "debug"; firmware-name = "j7-txpru0_1-fw"; }; + + icssg0_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 119 1>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; icssg1: icssg@b100000 { @@ -1923,5 +1933,15 @@ tx_pru1_1: txpru@c000 { reg-names = "iram", "control", "debug"; firmware-name = "j7-txpru1_1-fw"; }; + + icssg1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 120 4>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; };
The ICSSGs on K3 J721E SoCs contain an MDIO controller that can be used to control external PHYs associated with the Industrial Ethernet peripherals within each ICSSG instance. The MDIO module used within the ICSSG is similar to the MDIO Controller used in TI Davinci SoCs. A bus frequency of 1 MHz is chosen for the MDIO operations. The nodes are added and enabled in the common k3-j721e-main.dtsi file by default, and disabled in the existing J721E board dts file. These nodes need pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for ICSSG Ethernet. Any new board dts file should disable these if they are not sure. Signed-off-by: Suman Anna <s-anna@ti.com> --- .../dts/ti/k3-j721e-common-proc-board.dts | 8 ++++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 +++++++++++++++++++ 2 files changed, 28 insertions(+)