From patchwork Mon May 17 07:51:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fuad Tabba X-Patchwork-Id: 12261043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7609BC433B4 for ; Mon, 17 May 2021 07:57:51 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F031C60FF0 for ; Mon, 17 May 2021 07:57:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F031C60FF0 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Cc:To:From:Subject:References:Mime-Version: Message-Id:In-Reply-To:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zitqUcYo2BUqUVHA1lDTMVA0TZy7VH9rNjqSBZsaHI0=; b=LhRWDA7Gda8D6V /cxnEWXdLL3IKzbwkpdtsUq6kb4AbJ6uIFuIsooqqNb3emfuCYJTvgCo3YY4f9/L0u2A1uFlFm8k2 tNrHKDapmMScwrm+EgQH1OW3jdwX0Wt1cealNTiwY8zTdH6wMueoHKN0wNkbKak7DR9uKqPDVqykQ mYle/t0bTceo0VBYKmztfqA0C2jkoAqeuKSc3Wz+doeeqlobZnvpvIh5JWgs2uSZO+fePye+OlLpv mkThJGQZgLf0W684U5+kxp7PfqhMtTYeLp2t/bEgfo5YKfprRW45lccyjH4ZZtlDPs9iIpoQwlOB2 EvweqigHBRRf5GGzYjAg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1liY6B-00E7Qc-6M; Mon, 17 May 2021 07:55:43 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1liY2K-00E6Vo-Q2 for linux-arm-kernel@desiato.infradead.org; Mon, 17 May 2021 07:51:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=Content-Type:Cc:To:From:Subject: References:Mime-Version:Message-Id:In-Reply-To:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=3fD2bGajdocFk7ES4jFUnMkgXuo5scqSJn5Icu9/qYQ=; b=r3OPoTA/cdF3j6cmG6NMTpzALa qAvQ8noH5LFcsdXKbcVfm4tzoVAKnYARI+yECLlItpKY8heKNq7Ojr8lbQ6C40c1iWWVwKc6YAHwS 4gYr99q78mQXRi9gaN7eHClS7bDsKlVWGMW8ZYkdEThChaUj6hDdEXXyhIW5QIBZ48brnwpm+F4TZ RiEPoLMlXx2Yzx1plWNfhlrjx5wp7LYjwo1L+eMkUivBPcIxM3VEQq9ATAAWlpWUmGzhK1m6AkMl2 30HVO0t/jLeTu9CxJzM0N7Qud49fPePmFhtQgweXhdWVtGzzdEdF70A1Gntlcc5276qruzorD7agt 4vlna5dw==; Received: from mail-wm1-x349.google.com ([2a00:1450:4864:20::349]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1liY2H-00DYvL-M5 for linux-arm-kernel@lists.infradead.org; Mon, 17 May 2021 07:51:35 +0000 Received: by mail-wm1-x349.google.com with SMTP id x7-20020a7bc2070000b0290149dcabfd85so1100105wmi.8 for ; Mon, 17 May 2021 00:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=3fD2bGajdocFk7ES4jFUnMkgXuo5scqSJn5Icu9/qYQ=; b=TbMCk1vh5qr7S/gsLJewtveFG21nl+lZnuaT5mmUtWFHrhGBN8wHHzmIwoqdX/ZFFW zVbd0MWD7LaCdostNCARBa4JUsf/inmQp0xQ7Ks+7/SyQchDihTAwQUKTPD5w3rhjq55 nYgEeVqqeJdw03aLWng71m0MYhY6GYm7aeFDXUZQf3aAptUSRWr+RVPgOdzgezLfhLIn UrxeZD/4vnfzew2BTNBjQ+a+AEZr2xrRkrVObvjEMrCyrbJ/o2yZasWXjJrG0oQPMqNB dUWjI1mi+V7fatkrdiYD019eiSPh3zw5KuyrWxEqtxNNyIXkOUmSdjJ6SXZR+31SUNuL +Qfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=3fD2bGajdocFk7ES4jFUnMkgXuo5scqSJn5Icu9/qYQ=; b=BalyIWEhlHdiXUK9nDb44br35bStUqm/waEObwVFMJGTCsMO81jGPZSxs7LJ27/kPY 8ZJ2Wmx/o5GyyC+mnGkeK07dzTsGHiYzmZZH5YT+ezWoPpYIJZgv7t3jSCr8lavrFJAf 5Hz7Ll3XmYGjbsSuPTRAp6NmJ8m+Lq0apN1OE7FWqGEWroF620pwAOUVfWILGKzSZgMY XhdbSuwup4C6wO4khIrByE4xfkyhcU0f8TbUEuFxSe6pQnMUtaTPmdUHBIO2+Ltuir8g 1ZJ7xW+Nf8w9QWgFoQnjXe2G53BYk4P/uZED+fVAm8KrDwA0jszlAMSErKlNuIejsWqa QaeA== X-Gm-Message-State: AOAM533uSpEvRV3e/mstF/DAxxQ8gd89UGFppXA4B0chsl+mmIff+KFq 3zsnG26eose5fI7zzMb+sRP3W6dxlOskHESRepfHsYh3qh1Nsn2YdWfjTrX5bbsMARUSTyrC83z QRxYMOugVrvspEyAwcSTf0zu4U5KTkBvnxsAEwiwee/VlFrg9KehKxbPsRgqQcHdaeGDgWoPsB3 k9Xw== X-Google-Smtp-Source: ABdhPJxuuYaV1u+hmFMMYD3uPf7jZy4GZ1A9Ac5ST2LTHC7meNBpZeBqSLWOdeAcX5/y4sj9sn0is7Rxaw== X-Received: from tabba.c.googlers.com ([fda3:e722:ac3:10:28:9cb1:c0a8:482]) (user=tabba job=sendgmr) by 2002:a7b:cb0b:: with SMTP id u11mr1994821wmj.0.1621237890277; Mon, 17 May 2021 00:51:30 -0700 (PDT) Date: Mon, 17 May 2021 08:51:10 +0100 In-Reply-To: <20210517075124.152151-1-tabba@google.com> Message-Id: <20210517075124.152151-3-tabba@google.com> Mime-Version: 1.0 References: <20210517075124.152151-1-tabba@google.com> X-Mailer: git-send-email 2.31.1.751.gd2f1c929bd-goog Subject: [PATCH v2 02/16] arm64: Do not enable uaccess for flush_icache_range From: Fuad Tabba To: linux-arm-kernel@lists.infradead.org Cc: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, maz@kernel.org, ardb@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, robin.murphy@arm.com, tabba@google.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210517_005133_745641_ED6F9727 X-CRM114-Status: GOOD ( 13.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org __flush_icache_range works on the kernel linear map, and doesn't need uaccess. The existing code is a side-effect of its current implementation with __flush_cache_user_range fallthrough. Instead of fallthrough to share the code, use a common macro for the two where the caller can specify whether user-space access is needed. No functional change intended. Possible performance impact due to the reduced number of instructions. Reported-by: Catalin Marinas Reported-by: Will Deacon Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/ Signed-off-by: Fuad Tabba --- arch/arm64/include/asm/assembler.h | 13 ++++-- arch/arm64/mm/cache.S | 64 +++++++++++++++++++++--------- 2 files changed, 54 insertions(+), 23 deletions(-) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 8418c1bd8f04..6ff7a3a3b238 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -426,16 +426,21 @@ alternative_endif * Macro to perform an instruction cache maintenance for the interval * [start, end) * - * start, end: virtual addresses describing the region - * label: A label to branch to on user fault. - * Corrupts: tmp1, tmp2 + * start, end: virtual addresses describing the region + * needs_uaccess: might access user space memory + * label: label to branch to on user fault (if needs_uaccess) + * Corrupts: tmp1, tmp2 */ - .macro invalidate_icache_by_line start, end, tmp1, tmp2, label + .macro invalidate_icache_by_line start, end, tmp1, tmp2, needs_uaccess, label icache_line_size \tmp1, \tmp2 sub \tmp2, \tmp1, #1 bic \tmp2, \start, \tmp2 9997: + .if \needs_uaccess USER(\label, ic ivau, \tmp2) // invalidate I line PoU + .else + ic ivau, \tmp2 + .endif add \tmp2, \tmp2, \tmp1 cmp \tmp2, \end b.lo 9997b diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 2d881f34dd9d..092f73acdf9a 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -15,30 +15,20 @@ #include /* - * flush_icache_range(start,end) + * __flush_cache_range(start,end) [needs_uaccess] * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, * and will be executed. * - * - start - virtual start address of region - * - end - virtual end address of region + * - start - virtual start address of region + * - end - virtual end address of region + * - needs_uaccess - (macro parameter) might access user space memory */ -SYM_FUNC_START(__flush_icache_range) - /* FALLTHROUGH */ - -/* - * __flush_cache_user_range(start,end) - * - * Ensure that the I and D caches are coherent within specified region. - * This is typically used when code has been written to a memory region, - * and will be executed. - * - * - start - virtual start address of region - * - end - virtual end address of region - */ -SYM_FUNC_START(__flush_cache_user_range) +.macro __flush_cache_range, needs_uaccess + .if \needs_uaccess uaccess_ttbr0_enable x2, x3, x4 + .endif alternative_if ARM64_HAS_CACHE_IDC dsb ishst b 7f @@ -47,7 +37,11 @@ alternative_else_nop_endif sub x3, x2, #1 bic x4, x0, x3 1: + .if \needs_uaccess user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE + .else +alternative_insn "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE + .endif add x4, x4, x2 cmp x4, x1 b.lo 1b @@ -58,15 +52,47 @@ alternative_if ARM64_HAS_CACHE_DIC isb b 8f alternative_else_nop_endif - invalidate_icache_by_line x0, x1, x2, x3, 9f + invalidate_icache_by_line x0, x1, x2, x3, \needs_uaccess, 9f 8: mov x0, #0 1: + .if \needs_uaccess uaccess_ttbr0_disable x1, x2 + .endif ret + + .if \needs_uaccess 9: mov x0, #-EFAULT b 1b + .endif +.endm + +/* + * flush_icache_range(start,end) + * + * Ensure that the I and D caches are coherent within specified region. + * This is typically used when code has been written to a memory region, + * and will be executed. + * + * - start - virtual start address of region + * - end - virtual end address of region + */ +SYM_FUNC_START(__flush_icache_range) + __flush_cache_range needs_uaccess=0 SYM_FUNC_END(__flush_icache_range) + +/* + * __flush_cache_user_range(start,end) + * + * Ensure that the I and D caches are coherent within specified region. + * This is typically used when code has been written to a memory region, + * and will be executed. + * + * - start - virtual start address of region + * - end - virtual end address of region + */ +SYM_FUNC_START(__flush_cache_user_range) + __flush_cache_range needs_uaccess=1 SYM_FUNC_END(__flush_cache_user_range) /* @@ -86,7 +112,7 @@ alternative_else_nop_endif uaccess_ttbr0_enable x2, x3, x4 - invalidate_icache_by_line x0, x1, x2, x3, 2f + invalidate_icache_by_line x0, x1, x2, x3, 1, 2f mov x0, xzr 1: uaccess_ttbr0_disable x1, x2