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bh=RWXPMPgEuCU/3b7hbbrURn9Chl/0n89KN/Wk7Q6xjkE=; b=ARZUQDrpyeCL4eGA4Ci+kblyxNLBJvJnRbpGO18zXBuTzr+Zr+jz5D1t+zK/kCAHUj t1KCmmd760ADxMBOI7PWEb+fedNmtGsRf53kY9/R3ItBRbUpjjoDhpQvB/9tqpqFn9KR b5NitaUlqbJ5SSic+Jq1X2euYg+1zlK+R3Lbs8ShSxf5TM8OPDm7JHw+H7b3+CeNLwBr pGr74sPwz95GdD4dJ7YIihWfHTzLcIgceKjQhVH79f9Bvo5NGWhCJPxMYD+AcFupXrjf +xtq/LeGdL3lb/a2y3WRuhjKnTdMe20w9d8jiJfDm7U3qs+RDDU9mzq/3PgQ9YyU0Vax AJpw== X-Gm-Message-State: AOAM530+TYOhDIJTO2z9+dHkKvQ79vd3hNsGHIbTWSMkM9cQ4VjtaWe+ 6aMPX0ai4qL7y6hJrCO7AKGo0HmVuf1G X-Google-Smtp-Source: ABdhPJwhvrPdqkLsHHWGfUDUXsyPzwAmuX2finWkvCnTk1TAyQjlCyOHtAZMnfqYlVztEuaxyYv0a7IRY9S+ X-Received: from eugenis.svl.corp.google.com ([2620:15c:2ce:200:b800:442e:78b7:3fac]) (user=eugenis job=sendgmr) by 2002:a25:b701:: with SMTP id t1mr3595486ybj.348.1621476196428; Wed, 19 May 2021 19:03:16 -0700 (PDT) Date: Wed, 19 May 2021 19:03:05 -0700 Message-Id: <20210520020305.2826694-1-eugenis@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.31.1.751.gd2f1c929bd-goog Subject: [PATCH v4] kasan: speed up mte_set_mem_tag_range From: Evgenii Stepanov To: Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Dmitry Vyukov , Catalin Marinas , Will Deacon , Steven Price , Peter Collingbourne , Evgenii Stepanov , kasan-dev@googlegroups.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210519_190320_240648_EA77AF0E X-CRM114-Status: GOOD ( 20.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use DC GVA / DC GZVA to speed up KASan memory tagging in HW tags mode. The first cacheline is always tagged using STG/STZG even if the address is cacheline-aligned, as benchmarks show it is faster than a conditional branch. Signed-off-by: Evgenii Stepanov Co-developed-by: Peter Collingbourne Signed-off-by: Peter Collingbourne Reviewed-by: Catalin Marinas --- Changelog since v1: - Added Co-developed-by. Changelog since v2: - Added Signed-off-by. Changelog since v3: - Move the implementation back to C with a bit of inline asm. arch/arm64/include/asm/mte-kasan.h | 98 +++++++++++++++++++++--------- 1 file changed, 70 insertions(+), 28 deletions(-) diff --git a/arch/arm64/include/asm/mte-kasan.h b/arch/arm64/include/asm/mte-kasan.h index ddd4d17cf9a0..34e23886f346 100644 --- a/arch/arm64/include/asm/mte-kasan.h +++ b/arch/arm64/include/asm/mte-kasan.h @@ -48,43 +48,85 @@ static inline u8 mte_get_random_tag(void) return mte_get_ptr_tag(addr); } +static inline u64 __stg_post(u64 p) +{ + asm volatile(__MTE_PREAMBLE "stg %0, [%0], #16" + : "+r"(p) + : + : "memory"); + return p; +} + +static inline u64 __stzg_post(u64 p) +{ + asm volatile(__MTE_PREAMBLE "stzg %0, [%0], #16" + : "+r"(p) + : + : "memory"); + return p; +} + +static inline void __dc_gva(u64 p) +{ + asm volatile(__MTE_PREAMBLE "dc gva, %0" : : "r"(p) : "memory"); +} + +static inline void __dc_gzva(u64 p) +{ + asm volatile(__MTE_PREAMBLE "dc gzva, %0" : : "r"(p) : "memory"); +} + /* * Assign allocation tags for a region of memory based on the pointer tag. * Note: The address must be non-NULL and MTE_GRANULE_SIZE aligned and - * size must be non-zero and MTE_GRANULE_SIZE aligned. + * size must be MTE_GRANULE_SIZE aligned. */ -static inline void mte_set_mem_tag_range(void *addr, size_t size, - u8 tag, bool init) +static inline void mte_set_mem_tag_range(void *addr, size_t size, u8 tag, + bool init) { - u64 curr, end; + u64 curr, DCZID, mask, line_size, end1, end2, end3; - if (!size) - return; + /* Read DC G(Z)VA store size from the register. */ + __asm__ __volatile__(__MTE_PREAMBLE "mrs %0, dczid_el0" + : "=r"(DCZID)::); + line_size = 4ul << (DCZID & 0xf); curr = (u64)__tag_set(addr, tag); - end = curr + size; - - /* - * 'asm volatile' is required to prevent the compiler to move - * the statement outside of the loop. + mask = line_size - 1; + /* STG/STZG up to the end of the first cache line. */ + end1 = curr | mask; + end3 = curr + size; + /* DC GVA / GZVA in [end1, end2) */ + end2 = end3 & ~mask; + + /* The following code uses STG on the first cache line even if the start + * address is cache line aligned - it appears to be faster than an + * alignment check + conditional branch. Also, if the size is at least 2 + * cache lines, the first two loops can use post-condition to save one + * branch each. */ - if (init) { - do { - asm volatile(__MTE_PREAMBLE "stzg %0, [%0]" - : - : "r" (curr) - : "memory"); - curr += MTE_GRANULE_SIZE; - } while (curr != end); - } else { - do { - asm volatile(__MTE_PREAMBLE "stg %0, [%0]" - : - : "r" (curr) - : "memory"); - curr += MTE_GRANULE_SIZE; - } while (curr != end); - } +#define SET_MEMTAG_RANGE(stg_post, dc_gva) \ + do { \ + if (size >= 2 * line_size) { \ + do { \ + curr = stg_post(curr); \ + } while (curr < end1); \ + \ + do { \ + dc_gva(curr); \ + curr += line_size; \ + } while (curr < end2); \ + } \ + \ + while (curr < end3) \ + curr = stg_post(curr); \ + } while (0) + + if (init) + SET_MEMTAG_RANGE(__stzg_post, __dc_gzva); + else + SET_MEMTAG_RANGE(__stg_post, __dc_gva); +#undef SET_MEMTAG_RANGE } void mte_enable_kernel_sync(void);