diff mbox series

[V6,2/4] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL

Message ID 20210522134249.15322-3-peng.fan@oss.nxp.com (mailing list archive)
State New, archived
Headers show
Series soc: imx: add i.MX BLK-CTL support | expand

Commit Message

Peng Fan (OSS) May 22, 2021, 1:42 p.m. UTC
From: Peng Fan <peng.fan@nxp.com>

Document the i.MX BLK_CTL with its devicetree properties.

Each BLK CTL have different power domain inputs and they have different
names, so we are not able to list all the power domain names for each
BLK CTL here.

For example:
i.MX8MM dispmix BLK CTL, it has
	power-domains = <&pgc_dispmix>, <&pgc_mipi>;
	power-domain-names = "dispmix", "mipi";

vpumix BLK CTL, it has
	power-domains = <&vpumix_pd>, <&vpu_g1_pd>, <&vpu_g2_pd>,
			<&vpu_h1_pd>;
	power-domain-names = "vpumix", "g1", "g2", "h1";

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../bindings/soc/imx/fsl,imx-blk-ctl.yaml     | 66 +++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml

Comments

Shawn Guo June 12, 2021, 12:45 a.m. UTC | #1
On Sat, May 22, 2021 at 09:42:47PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Document the i.MX BLK_CTL with its devicetree properties.
> 
> Each BLK CTL have different power domain inputs and they have different
> names, so we are not able to list all the power domain names for each
> BLK CTL here.
> 
> For example:
> i.MX8MM dispmix BLK CTL, it has
> 	power-domains = <&pgc_dispmix>, <&pgc_mipi>;
> 	power-domain-names = "dispmix", "mipi";
> 
> vpumix BLK CTL, it has
> 	power-domains = <&vpumix_pd>, <&vpu_g1_pd>, <&vpu_g2_pd>,
> 			<&vpu_h1_pd>;
> 	power-domain-names = "vpumix", "g1", "g2", "h1";
> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Can we be consistent in using 'dt-bindings: ...' as prefix?

Shawn

> ---
>  .../bindings/soc/imx/fsl,imx-blk-ctl.yaml     | 66 +++++++++++++++++++
>  1 file changed, 66 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
> new file mode 100644
> index 000000000000..a66f11acc6b4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/imx/fsl,imx-blk-ctl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX BLK_CTL
> +
> +maintainers:
> +  - Peng Fan <peng.fan@nxp.com>
> +
> +description:
> +  i.MX BLK_CTL is a conglomerate of different GPRs that are
> +  dedicated to a specific subsystem. It usually contains
> +  clocks and resets amongst other things. Here we take the clocks
> +  and resets as virtual PDs, the reason we could not take it as
> +  clock provider is there is A/B lock issue between power domain
> +  and clock.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - fsl,imx8mm-dispmix-blk-ctl
> +          - fsl,imx8mm-vpumix-blk-ctl
> +      - const: syscon
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#power-domain-cells":
> +    const: 1
> +
> +  power-domains:
> +    minItems: 1
> +    maxItems: 32
> +
> +  power-domain-names:
> +    minItems: 1
> +    maxItems: 32
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 32
> +
> +required:
> +  - compatible
> +  - reg
> +  - power-domains
> +  - power-domain-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/imx8mm-clock.h>
> +
> +    dispmix_blk_ctl: blk-ctl@32e28000 {
> +      compatible = "fsl,imx8mm-dispmix-blk-ctl", "syscon";
> +      reg = <0x32e28000 0x100>;
> +      #power-domain-cells = <1>;
> +      power-domains = <&pgc_dispmix>, <&pgc_mipi>;
> +      power-domain-names = "dispmix", "mipi";
> +      clocks = <&clk IMX8MM_CLK_DISP_ROOT>, <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
> +               <&clk IMX8MM_CLK_DISP_APB_ROOT>;
> +    };
> -- 
> 2.30.0
>
Peng Fan (OSS) June 12, 2021, 12:20 p.m. UTC | #2
> Subject: Re: [PATCH V6 2/4] Documentation: bindings: clk: Add bindings for
> i.MX BLK_CTL
> 
> On Sat, May 22, 2021 at 09:42:47PM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Document the i.MX BLK_CTL with its devicetree properties.
> >
> > Each BLK CTL have different power domain inputs and they have
> > different names, so we are not able to list all the power domain names
> > for each BLK CTL here.
> >
> > For example:
> > i.MX8MM dispmix BLK CTL, it has
> > 	power-domains = <&pgc_dispmix>, <&pgc_mipi>;
> > 	power-domain-names = "dispmix", "mipi";
> >
> > vpumix BLK CTL, it has
> > 	power-domains = <&vpumix_pd>, <&vpu_g1_pd>, <&vpu_g2_pd>,
> > 			<&vpu_h1_pd>;
> > 	power-domain-names = "vpumix", "g1", "g2", "h1";
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> 
> Can we be consistent in using 'dt-bindings: ...' as prefix?

Yes. Fix in v7.

Thanks,
Peng.

> 
> Shawn
> 
> > ---
> >  .../bindings/soc/imx/fsl,imx-blk-ctl.yaml     | 66
> +++++++++++++++++++
> >  1 file changed, 66 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
> > b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
> > new file mode 100644
> > index 000000000000..a66f11acc6b4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
> > @@ -0,0 +1,66 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fschemas%2Fsoc%2Fimx%2Ffsl%2Cimx-blk-ctl.yaml%23&amp;
> data
> >
> +=04%7C01%7Cpeng.fan%40nxp.com%7C8ef49946599c41046e5308d92d3b7
> 2df%7C68
> >
> +6ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637590555623663011%
> 7CUnknown
> >
> +%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha
> WwiLC
> >
> +JXVCI6Mn0%3D%7C1000&amp;sdata=%2FvyX8r5Dc0nWjRaLASXKvs7JGKuP
> 4iwMQPMNa
> > +u93SH4%3D&amp;reserved=0
> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cpe
> ng.fan%
> >
> +40nxp.com%7C8ef49946599c41046e5308d92d3b72df%7C686ea1d3bc2b4c
> 6fa92cd9
> >
> +9c5c301635%7C0%7C0%7C637590555623663011%7CUnknown%7CTWFpb
> GZsb3d8eyJWI
> >
> +joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7
> C1000&
> >
> +amp;sdata=j25%2F6NIDdiN3weLr0xMDM5z91P9KXDLEzIRlf7A4OPs%3D&a
> mp;reserv
> > +ed=0
> > +
> > +title: NXP i.MX BLK_CTL
> > +
> > +maintainers:
> > +  - Peng Fan <peng.fan@nxp.com>
> > +
> > +description:
> > +  i.MX BLK_CTL is a conglomerate of different GPRs that are
> > +  dedicated to a specific subsystem. It usually contains
> > +  clocks and resets amongst other things. Here we take the clocks
> > +  and resets as virtual PDs, the reason we could not take it as
> > +  clock provider is there is A/B lock issue between power domain
> > +  and clock.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - fsl,imx8mm-dispmix-blk-ctl
> > +          - fsl,imx8mm-vpumix-blk-ctl
> > +      - const: syscon
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  "#power-domain-cells":
> > +    const: 1
> > +
> > +  power-domains:
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  power-domain-names:
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  clocks:
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - power-domains
> > +  - power-domain-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/imx8mm-clock.h>
> > +
> > +    dispmix_blk_ctl: blk-ctl@32e28000 {
> > +      compatible = "fsl,imx8mm-dispmix-blk-ctl", "syscon";
> > +      reg = <0x32e28000 0x100>;
> > +      #power-domain-cells = <1>;
> > +      power-domains = <&pgc_dispmix>, <&pgc_mipi>;
> > +      power-domain-names = "dispmix", "mipi";
> > +      clocks = <&clk IMX8MM_CLK_DISP_ROOT>, <&clk
> IMX8MM_CLK_DISP_AXI_ROOT>,
> > +               <&clk IMX8MM_CLK_DISP_APB_ROOT>;
> > +    };
> > --
> > 2.30.0
> >
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
new file mode 100644
index 000000000000..a66f11acc6b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml
@@ -0,0 +1,66 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx-blk-ctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX BLK_CTL
+
+maintainers:
+  - Peng Fan <peng.fan@nxp.com>
+
+description:
+  i.MX BLK_CTL is a conglomerate of different GPRs that are
+  dedicated to a specific subsystem. It usually contains
+  clocks and resets amongst other things. Here we take the clocks
+  and resets as virtual PDs, the reason we could not take it as
+  clock provider is there is A/B lock issue between power domain
+  and clock.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - fsl,imx8mm-dispmix-blk-ctl
+          - fsl,imx8mm-vpumix-blk-ctl
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  "#power-domain-cells":
+    const: 1
+
+  power-domains:
+    minItems: 1
+    maxItems: 32
+
+  power-domain-names:
+    minItems: 1
+    maxItems: 32
+
+  clocks:
+    minItems: 1
+    maxItems: 32
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - power-domain-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+
+    dispmix_blk_ctl: blk-ctl@32e28000 {
+      compatible = "fsl,imx8mm-dispmix-blk-ctl", "syscon";
+      reg = <0x32e28000 0x100>;
+      #power-domain-cells = <1>;
+      power-domains = <&pgc_dispmix>, <&pgc_mipi>;
+      power-domain-names = "dispmix", "mipi";
+      clocks = <&clk IMX8MM_CLK_DISP_ROOT>, <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+               <&clk IMX8MM_CLK_DISP_APB_ROOT>;
+    };