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[2003:f1:370a:3a00:f22f:74ff:fe21:725]) by smtp.googlemail.com with ESMTPSA id n24sm9162451edv.51.2021.05.24.03.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 03:45:46 -0700 (PDT) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: narmstrong@baylibre.com, mturquette@baylibre.com, sboyd@kernel.org, khilman@baylibre.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH] clk: meson: meson8b: Don't use MPLL1 as parent of vclk_in_sel Date: Mon, 24 May 2021 12:45:33 +0200 Message-Id: <20210524104533.555953-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_034549_833643_4D7917DD X-CRM114-Status: GOOD ( 13.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MPLL1 is needed for audio output. Drop it from the vclk_in_sel parent list so we only use the (mutable) vid_pll_final_div tree or one of the (fixed) FCLK_DIV{3,4,5} clocks. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index a844d35b553a..f8bd211db720 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1154,6 +1154,10 @@ static struct clk_regmap meson8b_vid_pll_final_div = { }, }; +/* + * parent 0x6 is meson8b_mpll1 but we don't use it here because it's reserved + * for the audio outputs. + */ static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { &meson8b_vid_pll_final_div.hw, &meson8b_fclk_div4.hw, @@ -1161,7 +1165,6 @@ static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { &meson8b_fclk_div5.hw, &meson8b_vid_pll_final_div.hw, &meson8b_fclk_div7.hw, - &meson8b_mpll1.hw, }; static struct clk_regmap meson8b_vclk_in_sel = {