From patchwork Tue May 25 06:25:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaxson Han X-Patchwork-Id: 12277989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 779D9C2B9F8 for ; Tue, 25 May 2021 06:28:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42981610FC for ; Tue, 25 May 2021 06:28:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 42981610FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2fzdSpVP95tTn8hcut7al3ftfUj825L47GNZ0gGpChQ=; b=RjeEuJZZXnsMSb enoYsw1bIJue7WMzyatjpgRrxNeOG4gvyZOCVEGFgUYswBsi8dhbgRxSqS09kZW2ct0gScWF8kvWd tET5MGCZeC0N3zrW4F6fNnAKOpl4CrDqIE1Shk/NQKcDjb2iNXBrv/M1qZL90nxEvbZxGIShK9z8X NRczYKTsg+mPXBHGObDKsDOU2/df+JV6KW+ZhjG5EHXJoy7X8wkY+GR1qbRC7QumUfkoBHHDaKD2Y c/6wFH1ubOHH223CBr7+Vi34S+7xBgXsfNLhI4KDw2t0Ris7s3as9H74cKCTUV1J0z6iJ566fdmxX 9wHrn5UvKk58ISqVIYlg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQWo-003c7p-W8; Tue, 25 May 2021 06:26:59 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llQVd-003btr-Db for linux-arm-kernel@lists.infradead.org; Tue, 25 May 2021 06:25:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9175E1042; Mon, 24 May 2021 23:25:43 -0700 (PDT) Received: from optiplex-7070.shanghai.arm.com (optiplex-7070.shanghai.arm.com [10.169.188.115]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BB0C93F73D; Mon, 24 May 2021 23:25:41 -0700 (PDT) From: Jaxson Han To: mark.rutland@arm.com, andre.przywara@arm.com Cc: linux-arm-kernel@lists.infradead.org, wei.chen@arm.com, jaxson.han@arm.com Subject: [boot-wrapper PATCH v3 6/8] gic-v3: Prepare for gicv3 with EL2 Date: Tue, 25 May 2021 14:25:07 +0800 Message-Id: <20210525062509.201464-7-jaxson.han@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210525062509.201464-1-jaxson.han@arm.com> References: <20210525062509.201464-1-jaxson.han@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_232545_579772_DA000FF7 X-CRM114-Status: GOOD ( 11.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a preparation for allowing boot-wrapper configuring the gicv3 with EL2. When confiuring with EL2, since there is no ICC_CTLR_EL2, the ICC_CTLR_EL3 cannot be replaced with ICC_CTLR_EL2 simply. See [https://developer.arm.com/documentation/ihi0069/latest/]. As the caller, gic_secure_init expects the ICC_CTLR to be written, we change the function into gic_init_icc_ctlr(). In the GIC spec, the r/w bits in this register ([6:0]) either affect EL3 IRQ routing (not applicable since no EL3), non-secure IRQ handling (not applicable since only secure state in Armv8-R aarch64), or are aliased to ICC_CTLR_EL1 bits. So, based on this, the new gic_init_icc_ctlr() would be: When currentEL is EL3, init ICC_CTLR_EL3 as before. When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET. Signed-off-by: Jaxson Han Reviewed-by: Andre Przywara --- arch/aarch32/include/asm/gic-v3.h | 7 ++++++ arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++--- gic-v3.c | 2 +- 3 files changed, 43 insertions(+), 4 deletions(-) diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h index ec9a327..86abe09 100644 --- a/arch/aarch32/include/asm/gic-v3.h +++ b/arch/aarch32/include/asm/gic-v3.h @@ -9,6 +9,8 @@ #ifndef __ASM_AARCH32_GICV3_H #define __ASM_AARCH32_GICV3_H +#define ICC_CTLR_RESET (0UL) + static inline uint32_t gic_read_icc_sre(void) { uint32_t val; @@ -26,4 +28,9 @@ static inline void gic_write_icc_ctlr(uint32_t val) asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val)); } +static inline void gic_init_icc_ctlr() +{ + gic_write_icc_ctlr(ICC_CTLR_RESET); +} + #endif diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h index e743c02..b3dfbd3 100644 --- a/arch/aarch64/include/asm/gic-v3.h +++ b/arch/aarch64/include/asm/gic-v3.h @@ -15,21 +15,53 @@ #define ICC_CTLR_EL3 "S3_6_C12_C12_4" #define ICC_PMR_EL1 "S3_0_C4_C6_0" +#define ICC_CTLR_EL3_RESET (0UL) +#define ICC_CTLR_EL1_RESET (0UL) + +static inline uint32_t current_el(void) +{ + uint32_t val; + + asm volatile ("mrs %0, CurrentEL" : "=r" (val)); + return val; +} + static inline uint32_t gic_read_icc_sre(void) { uint32_t val; - asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val)); + + if(current_el() == CURRENTEL_EL3) + asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val)); + else + asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val)); + return val; } static inline void gic_write_icc_sre(uint32_t val) { - asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); + if(current_el() == CURRENTEL_EL3) + asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val)); + else + asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val)); } -static inline void gic_write_icc_ctlr(uint32_t val) +static inline void gic_write_icc_ctlr_el3(uint32_t val) { asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val)); } +static inline void gic_write_icc_ctlr_el1(uint32_t val) +{ + asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val)); +} + +static inline void gic_init_icc_ctlr() +{ + if(current_el() == CURRENTEL_EL3) + gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET); + else + gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET); +} + #endif diff --git a/gic-v3.c b/gic-v3.c index ae2d2bc..4850572 100644 --- a/gic-v3.c +++ b/gic-v3.c @@ -121,6 +121,6 @@ void gic_secure_init(void) gic_write_icc_sre(sre); isb(); - gic_write_icc_ctlr(0); + gic_init_icc_ctlr(); isb(); }